On-Chip Microwave Filters on Standard Silicon Substrate Incorporating a Low-k BCB Dielectric Layer

Author(s):  
Lydia L. W. Leung ◽  
Kevin J. Chen ◽  
Xiao Huo ◽  
Philip C. H. Chan
2003 ◽  
Vol 40 (1) ◽  
pp. 9-11 ◽  
Author(s):  
Lydia L. W. Leung ◽  
Kevin J. Chen ◽  
Xiao Huo ◽  
Philip C. H. Chan

2003 ◽  
Vol 766 ◽  
Author(s):  
Ahila Krishnamoorthy ◽  
N.Y. Huang ◽  
Shu-Yunn Chong

AbstractBlack DiamondTM. (BD) is one of the primary candidates for use in copper-low k integration. Although BD is SiO2 based, it is vastly different from oxide in terms of dielectric strength and reliability. One of the main reliability concerns is the drift of copper ions under electric field to the surrounding dielectric layer and this is evaluated by voltage ramp (V-ramp) and time dependent dielectric breakdown (TDDB). Metal 1 and Metal 2 intralevel comb structures with different metal widths and spaces were chosen for dielectric breakdown studies. Breakdown field of individual test structures were obtained from V-ramp tests in the temperature range of 30 to 150°C. TDDB was performed in the field range 0.5 – 2 MV/cm. From the leakage between combs at the same level (either metal 1 or metal 2) Cu drift through SiC/BD or SiN/BD interface was characterized. It was found that Cu/barrier and barrier/low k interfaces functioned as easy paths for copper drift thereby shorting the lines. Cu/SiC was found to provide a better interface than Cu/SiN.


1996 ◽  
Vol 427 ◽  
Author(s):  
H. J. Barth

AbstractToday different Al-fill techniques are used for the fill of submicron contacts and vias. The integration aspects of the most promising approaches, Al-reflow, cold/hot Al-planarization and high pressure Al-fill (Forcefill) are compared to the widely used W-plug technique. The filling properties are discussed with respect to future applications in ULSI devices. Special attention is given to the barrier stability in contacts and the influence on patterning. Various electrical data and reliability results are compared to metallizations with W-plugs. The implications of the Al-fill processes on chip design, especially on the size and shape of holes, the pattern density, the possibility of producing stacked contacts/vias and the metal to contact/via overlap are considered also. In an outlook for future developments, e.g. the introduction of low k dielectrics, the inverse metallization architecture with (dual) damascene interconnects and the emerging Cu metallizations, Alfill processes are facing new challenges which will be discussed.


2013 ◽  
Vol 592-593 ◽  
pp. 563-568
Author(s):  
Christoph Sander ◽  
Martin Gall ◽  
Kong Boon Yeap ◽  
Ehrenfried Zschech

Managing the emerging internal mechanical stress in chips particularly if they are 3D-tscked is a key task to maintain performance and reliability of microelectronic products. Hence, a strong need of a physics-based simulation methodology/flow emerges. This physics-based simulation, however, requires materials parameters with high accuracy. A full-chip analysis can then be performed, balancing the need for local resolution and computing time. Therefore, effective composite-type materials data for several regions of interest are needed. Advanced techniques to measure FEA-and design-relevant properties such as local and effective Youngs modulus and effective CTE values were developed and described in this paper. These data show a clear orientation dependence, caused by the chip design.


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