BISTs for post-bond test and electrical analysis of high density 3D interconnect defects

2018 ◽  
Author(s):  
Imed Jani ◽  
Didier Lattard ◽  
Pascal Vivet ◽  
Lucile Arnaud ◽  
Edith Beigne
Keyword(s):  
High Density ◽  
Electrical Analysis

SYSTEM-LEVEL, POST-LAYOUT ELECTRICAL ANALYSIS FOR HIGH-DENSITY ADVANCED PACKAGING

2019 ◽  
Vol 2019 (DPC) ◽  
pp. 000856-000877
Author(s):  
Tarek Ramadan
Keyword(s):  
Circuit Simulation ◽  
Timing Analysis ◽  
High Density ◽  
System Level ◽  
Static Timing Analysis ◽  
Package Design ◽  
Static Timing ◽  
Parasitic Extraction ◽  
Advanced Packaging ◽  
Electrical Analysis

INTRODUCTION High-density advanced packaging (HDAP) continues to be the promising “More” in the “More than Moore” approach for improved form factor, functionality, and integration of multiple dies built using different technology nodes. HDAP offerings from outsourced assembly and test (OSAT) companies and foundries are continuously increasing. However, the full commercial productization of such offerings will require the assurance of both an acceptable yield and correct (as intended) functionality. This assurance, like that for integrated circuits (ICs), will come from the availability of proven and qualified electronic design automation (EDA) tools and flows that can be used by the design houses to build HDAPs with the confidence that they are compliant with the foundry/OSAT requirements and recommendations. The need for and general concept of assembly design kits (ADKs) that provide proven, qualified flows for HDAPs has been previously discussed in multiple white papers. In addition, there have been analyses of the need for assembly-level layout vs. schematic (LVS) verification for HDAPs. Best practices for an assembly-level LVS process have been proposed, including the required inputs (data, formats, etc.), and likely hurdles and potential errors have been highlighted. There has even been discussion of how parasitic extraction could be achieved for packages. However, as HDAP technologies and flows mature, system-level designers want to know if package design rule checking (DRC), assembly-level LVS, and layout vs. layout (LVL) verification (die-to-package alignment, scaling, orientation, etc.) are sufficient to guarantee correct functionality and successful manufacturing of the HDAP. While this question may depend on how complicated the HDAP is, in general, the answer (for now) is no. As HDAP technologies become more and more similar to IC technologies, it is clear that, although the physical verification steps for HDAP may be considered good progress, they are only part of a much more comprehensive flow, one that must account for a more in-depth, system-level electrical analysis. Of course, at the same time, expanded EDA tool support is required to ensure fast, accurate, automated flows that ensure package designers can meet their market schedules and expectations. HDAP POST-LAYOUT ELECTRICAL ANALYSIS In the case of an HDAP design, the foundry/OSAT expects that each component is designed and validated to meet the required HDAP constraints and specifications. For an analog-based flow, the designer must simulate the HDAP system circuitry, including parasitics, to ensure it meets the intended performance specifications. For a digital-based flow, the designer must run static timing analysis (STA) on the complete HDAP system, including parasitics, to ensure it meets the overall system timing budget. From an EDA perspective, building an automated flow to support these checks/analyses provides assurance that these processes can occur in a consistent, repeatable manner while ensuring accuracy and minimizing runtime. In general, EDA approaches take one of two paths. SINGLE COCKPIT In the cockpit approach, an EDA supplier builds a single simulator infrastructure to support HDAP circuit simulation, parasitic extraction (PEX), and static timing analysis (STA). Although a single interface seems convenient, it forces the designer to use the same design tool for all components at all levels (die and package). This approach may be too restrictive, given that HDAP design and verification typically require the involvement of multiple groups with varying backgrounds and tool preferences. Although this approach would be useful when building “fully live” heterogeneous HDAPs (i.e., both die and package are under development simultaneously, and can both be edited for performance), this is rarely the case. More commonly, known good dies (which have already been taped out) are used to build an HDAP. TOOL-AGNOSTIC In the tool-agnostic approach, an EDA supplier enables the user to construct the needed system-level connectivity of the HDAP (including parasitics), regardless of which design tools are used to build any one die or the package. Once the system-level connectivity is available, it can be exported in the required format to any circuit simulation/STA tool to simulate or analyze the entire HDAP system. This approach introduces minimum disruption to existing tools/methodologies used for die and package design. This paper discusses the implementation of a system-level parasitic netlist process for the HDAP using the tool-agnostic approach.

The Electrical Analysis on Ultra High Density IO Fan-Out Design

2021 ◽  
Author(s):  
Po-I Wu ◽  
Ming-Fong Jhong ◽  
Hung-Chun Kuo ◽  
Chih-Yi Huang ◽  
Chen-Chao Wang
Keyword(s):  
High Density ◽  
Electrical Analysis

Planar defects in ordered (Ga,In)P

1988 ◽  
Vol 46 ◽  
pp. 902-903
Author(s):  
S. McKernan ◽  
C. B. Carter ◽  
D. Bour ◽  
J. R. Shealy
Keyword(s):  
Electron Diffraction ◽  
Vapor Phase ◽  
Growth Direction ◽  
High Density ◽  
Ordered Structure ◽  
Planar Defects ◽  
Diffraction Patterns ◽  
Ternary Semiconductors ◽  
Anion Species ◽  
Metallic Vapor

The growth of ternary III-V semiconductors by organo-metallic vapor phase epitaxy (OMVPE) is widely practiced. It has been generally assumed that the resulting structure is the same as that of the corresponding binary semiconductors, but with the two different cation or anion species randomly distributed on their appropriate sublattice sites. Recently several different ternary semiconductors including AlxGa1-xAs, Gaxln-1-xAs and Gaxln1-xP1-6 have been observed in ordered states. A common feature of these ordered compounds is that they contain a relatively high density of defects. This is evident in electron diffraction patterns from these materials where streaks, which are typically parallel to the growth direction, are associated with the extra reflections arising from the ordering. However, where the (Ga,ln)P epilayer is reasonably well ordered the streaking is extremely faint, and the intensity of the ordered spot at 1/2(111) is much greater than that at 1/2(111). In these cases it is possible to image relatively clearly many of the defects found in the ordered structure.

Quantitative defect studies in semiconductor TEM samples prepared by low angle ion milling

1995 ◽  
Vol 53 ◽  
pp. 512-513
Author(s):  
L. Mulestagno ◽  
J.C. Holzer ◽  
P. Fraundorf
Keyword(s):  
Sample Preparation ◽  
Milling Time ◽  
High Density ◽  
Low Density ◽  
Ion Milling ◽  
High Quality ◽  
Variable Angle ◽  
Major Disadvantage ◽  
Induced Defects

Due to the wealth of information, both analytical and structural that can be obtained from it TEM always has been a favorite tool for the analysis of process-induced defects in semiconductor wafers. The only major disadvantage has always been, that the volume under study in the TEM is relatively small, making it difficult to locate low density defects, and sample preparation is a somewhat lengthy procedure. This problem has been somewhat alleviated by the availability of efficient low angle milling.Using a PIPS® variable angle ion -mill, manufactured by Gatan, we have been consistently obtaining planar specimens with a high quality thin area in excess of 5 × 104 μm2 in about half an hour (milling time), which has made it possible to locate defects at lower densities, or, for defects of relatively high density, obtain information which is statistically more significant (table 1).

Using the scanning electron microscope for failure analysis of high density magnetic media

1987 ◽  
Vol 45 ◽  
pp. 392-393
Author(s):  
Evelyn R. Ackerman ◽  
Gary D. Burnett
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Failure Analysis ◽  
High Density ◽  
Magnetic Media ◽  
Specific Data ◽  
Retrieval Systems ◽  
Operating Environments ◽  
The Media ◽  
Scanning Electron

Advancements in state of the art high density Head/Disk retrieval systems has increased the demand for sophisticated failure analysis methods. From 1968 to 1974 the emphasis was on the number of tracks per inch. (TPI) ranging from 100 to 400 as summarized in Table 1. This emphasis shifted with the increase in densities to include the number of bits per inch (BPI). A bit is formed by magnetizing the Fe203 particles of the media in one direction and allowing magnetic heads to recognize specific data patterns. From 1977 to 1986 the tracks per inch increased from 470 to 1400 corresponding to an increase from 6300 to 10,800 bits per inch respectively. Due to the reduction in the bit and track sizes, build and operating environments of systems have become critical factors in media reliability.Using the Ferrofluid pattern developing technique, the scanning electron microscope can be a valuable diagnostic tool in the examination of failure sites on disks.

Triglyceride to high density lipoprotein cholesterol ratio, total cholesterol to high density lipoprotein cholesterol ratio and low ankle brachial index in an elderly population

VASA ◽  
2014 ◽  
Vol 43 (3) ◽  
pp. 189-197 ◽  
Author(s):  
Yiqiang Zhan ◽  
Jinming Yu ◽  
Rongjing Ding ◽  
Yihong Sun ◽  
Dayi Hu
Keyword(s):  
High Density Lipoprotein ◽  
Total Cholesterol ◽  
High Density Lipoprotein Cholesterol ◽  
Ankle Brachial Index ◽  
Density Lipoprotein ◽  
High Density ◽  
Lipoprotein Cholesterol ◽  
Lipid Lowering ◽  
Cholesterol Ratio ◽  
Potential Biomarker

Background: The associations of triglyceride (TG) to high-density lipoprotein cholesterol ratio (HDL‑C) and total cholesterol (TC) to HDL‑C ratio and low ankle brachial index (ABI) were seldom investigated. Patients and methods: A population based cross-sectional survey was conducted and 2982 participants 60 years and over were recruited. TG, TC, HDL‑C, and low-density lipoprotein cholesterol (LDL-C) were assessed in all participants. Low ABI was defined as ABI ≤ 0.9 in either leg. Multiple logistic regression models were applied to study the association between TG/HDL‑C ratio, TC/HDL‑C ratio and low ABI. Results: The TG/HDL‑C ratios for those with ABI > 0.9 and ABI ≤ 0.9 were 1.28 ± 1.20 and 1.48 ± 1.13 (P < 0.0001), while the TC/HDL‑C ratios were 3.96 ± 1.09 and 4.32 ± 1.15 (P < 0.0001), respectively. After adjusting for age, gender, body mass index, obesity, current drinking, physical activity, hypertension, diabetes, lipid-lowering drugs, and cardiovascular disease history, the odds ratios (ORs) with 95 % confidence intervals (CIs) of low ABI for TG/HDL‑C ratio and TC/HDL‑C ratio were 1.10 (0.96, 1.26) and 1.34 (1.14, 1.59) in non-smokers. When TC was further adjusted, the ORs (95 % CIs) were 1.40 (0.79, 2.52) and 1.53 (1.21, 1.93) for TG/HDL‑C ratio and TC/HDL‑C ratio, respectively. Non-linear relationships were detected between TG/HDL‑C ratio and TC/HDL‑C ratio and low ABI in both smokers and non-smokers. Conclusions: TC/HDL‑C ratio was significantly associated with low ABI in non-smokers and the association was independent of TC, TG, HDL‑C, and LDL-C. TC/HDL‑C might be considered as a potential biomarker for early peripheral arterial disease screening.

Sign in / Sign up

Export Citation Format

Share Document