scholarly journals Single-Event Upset Analysis and Protection in High Speed Circuits

2006 ◽  
Author(s):  
M. Hosseinabady ◽  
P. Lotfi-Kamran ◽  
G. Di Natale ◽  
S. Di Carlo ◽  
A. Benso ◽  
...  
Keyword(s):  
High Speed ◽  
Single Event Upset ◽  
Single Event

SINGLE-EVENT EFFECTS IN III-V SEMICONDUCTOR ELECTRONICS

2004 ◽  
Vol 14 (02) ◽  
pp. 311-325 ◽  
Author(s):  
DALE McMORROW ◽  
JOSEPH S. MELINGER ◽  
ALVIN R. KNUDSON
Keyword(s):  
Energy Transfer ◽  
Integrated Circuits ◽  
Field Effect ◽  
High Speed ◽  
Field Effect Transistor ◽  
Single Event Upset ◽  
Single Event ◽  
Single Event Effects ◽  
Semiconductor Electronics ◽  
Effect Transistor

Single-event effects are a serious concern for high-speed III-V semiconductor devices operating in radiation-intense environments. GaAs integrated circuits (ICs) based on field effect transistor technology exhibit single-event upset sensitivity to protons and very low linear energy transfer (LET) particles. The current understanding of single-event effects in III-V circuits and devices, and approaches for mitigating their impact, are discussed.

scholarly journals Single-event upset studies of a high-speed digital optical data link

2001 ◽  
Vol 456 (3) ◽  
pp. 342-351 ◽  
Author(s):  
M.-L. Andrieux ◽  
J. Lundquist ◽  
B. Dinkespiler ◽  
G. Evans ◽  
L. Gallin-Martel ◽  
...  
Keyword(s):  
High Speed ◽  
Optical Data ◽  
Single Event Upset ◽  
Single Event ◽  
Data Link

scholarly journals Design and Analysis of SEU Hardened Latch for Low Power and High Speed Applications

2019 ◽  
Vol 9 (3) ◽  
pp. 21 ◽  
Author(s):  
Satheesh Kumar S ◽  
Kumaravel S
Keyword(s):  
Low Power ◽  
High Speed ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
High Energy ◽  
Oxide Semiconductor ◽  
High Energy Particle ◽  
Single Event Upset ◽  
Single Event ◽  
Clock Gating

Due to the reduction in technology scaling, gate capacitance and charge storage in sensitive nodes are rapidly decreasing, making Complementary Metal Oxide Semiconductor (CMOS) circuits more sensitive to soft errors caused by radiation. In this paper, a low-power and high-speed single event upset radiation hardened latch is proposed. The proposed latch can withstand single event upsets completely when the high energy particle hit on any one of its intermediate nodes. The proposed latch structure comprises of four CMOS feedback schemes and a Muller C-element with clock gating technique. For the sake of comparison, the proposed and the existing latches in the literature are implemented in 45nm CMOS technology. From the post layout simulation results, it may be noted that the proposed latch achieves 8% low power consumption, 95% less delay, and a 94% reduction in power-delay-product compared to the existing single event upset resilient and single event tolerant latches. Monte Carlo simulations show that the proposed latch is less sensitive to process, voltage, and temperature variations in comparison with the existing hardened latches in the literature.

RADIATION EFFECTS IN III-V SEMICONDUCTOR ELECTRONICS

2003 ◽  
Vol 13 (01) ◽  
pp. 293-326 ◽  
Author(s):  
B. D. WEAVER ◽  
DALE McMORROW ◽  
L. M. COHN
Keyword(s):  
High Speed ◽  
Radiation Effects ◽  
Semiconductor Devices ◽  
Damage Effect ◽  
High Electron ◽  
Single Event Upset ◽  
Single Event ◽  
Displacement Damage ◽  
Single Event Effects ◽  
Offset Voltage

Particle irradiation effects in III-V semiconductor devices and selected circuits are reviewed. Radiation effects concerns in III-V devices are associated primarily with displacement damage and single-event upset. In conventional transistors, displacement damage decreases the gain, increases leakage and shifts the collector-emitter offset voltage. In reduced dimensional devices. such as high electron mobility transistors and resonant tunneling diodes, the main displacement damage effect is to reduce current by increasing scattering out of the two-dimensional transport state. The current understanding of single-event effects in III-V circuits and devices, and approaches for mitigating their impact, are also discussed here. Single-event effects are a serious concern for high-speed III-V semiconductor devices operating in radiation-intense environments. GaAs integrated circuits (ICs) based on field effect transistor technology exhibit single-event upset sensitivity to protons and very low linear energy transfer (LET) particles; this sensitivity becomes more significant as clock rates and operating speeds increase.

scholarly journals Single-event upset studies of a high-speed digital optical data link

2000 ◽  
Author(s):  
Johan M. Lundquist ◽  
M-L. Andrieux ◽  
Bernard Dinkespiler ◽  
Gary A. Evans ◽  
L. Gallin-Martel ◽  
...  
Keyword(s):  
High Speed ◽  
Optical Data ◽  
Single Event Upset ◽  
Single Event ◽  
Data Link

SEU (Single Event Upset) Vulnerability of the Zilog Z-80 and NSC-800 Microprocessors,

1986 ◽  
Author(s):  
R. Koga ◽  
W. A. Kolasinski ◽  
C. King ◽  
J. Cusick
Keyword(s):  
Single Event Upset ◽  
Single Event
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