A Fast fc Automatic Tuning Circuit with Wide Tuning Range for WCDMA Direct Conversion Receiver Systems

2006 ◽  
Author(s):  
Osamu Watanabe ◽  
Rui Ito ◽  
Shigehito Saigusa ◽  
Tadashi Arai ◽  
Tetsuro Itakura
Keyword(s):  
Tuning Range ◽  
Direct Conversion ◽  
Automatic Tuning ◽  
Wide Tuning Range ◽  
Tuning Circuit

A Fast fc Automatic Tuning Circuit with Wide Tuning Range for WCDMA Direct Conversion Receiver Systems

2007 ◽  
Vol E90-C (6) ◽  
pp. 1247-1252
Author(s):  
O. WATANABE ◽  
R. ITO ◽  
S. SAIGUSA ◽  
T. ARAI ◽  
T. ITAKURA
Keyword(s):  
Tuning Range ◽  
Direct Conversion ◽  
Automatic Tuning ◽  
Wide Tuning Range ◽  
Tuning Circuit

scholarly journals A Novel Fast-Locking ADPLL Based on Bisection Method

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1382
Author(s):  
Xiaoying Deng ◽  
Huazhang Li ◽  
Mingcheng Zhu
Keyword(s):  
High Performance ◽  
Tuning Range ◽  
Frequency Control ◽  
Control Word ◽  
Cmos Process ◽  
Bisection Method ◽  
Reference Frequency ◽  
Wide Tuning Range ◽  
Cascade Structure ◽  
And Control

Based on the idea of bisection method, a new structure of All-Digital Phased-Locked Loop (ADPLL) with fast-locking is proposed. The structure and locking method are different from the traditional ADPLLs. The Control Circuit consists of frequency compare module, mode-adjust module and control module, which is responsible for adjusting the frequency control word of digital-controlled-oscillator (DCO) by Bisection method according to the result of the frequency compare between reference clock and restructure clock. With a high frequency cascade structure, the DCO achieves wide tuning range and high resolution. The proposed ADPLL was designed in SMIC 180 nm CMOS process. The measured results show a lock range of 640-to-1920 MHz with a 40 MHz reference frequency. The ADPLL core occupies 0.04 mm2, and the power consumption is 29.48 mW, with a 1.8 V supply. The longest locking time is 23 reference cycles, 575 ns, at 1.92 GHz. When the ADPLL operates at 1.28 GHz–1.6 GHz, the locking time is the shortest, only 9 reference cycles, 225 ns. Compared with the recent high-performance ADPLLs, our design shows advantages of small area, short locking time, and wide tuning range.

Modelling and analysis of a hybrid CS-CMOS ring VCO with wide tuning range

2020 ◽  
Vol 98 ◽  
pp. 104752 ◽  
Author(s):  
M. Maiti ◽  
A. Majumder ◽  
S. Chakrabartty ◽  
H. Song ◽  
B.K. Bhattacharyya
Keyword(s):  
Tuning Range ◽  
Wide Tuning Range

Wide-tuning range Si bipolar VCOs based on three-dimensional MMIC technology

1997 ◽  
Vol 45 (12) ◽  
pp. 2436-2443 ◽  
Author(s):  
K. Kamogawa ◽  
K. Nishikawa ◽  
C. Yamaguchi ◽  
M. Hirano ◽  
I. Toyoda ◽  
...  
Keyword(s):  
Tuning Range ◽  
Three Dimensional ◽  
Wide Tuning Range
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