Floating-Point Shadow Value Analysis

In this employee payroll application, if there is an error program there will be a loss for employees and the company. Losses for employees, if this application program error occurs then the salary reduction will experience delays due to the difficulty in the process of calculating employee salaries and employees will be late in receiving salaries. Losses for the company, if there is an error program in this application, the company will suffer losses if the employee wants a salary reduction quickly but the company cannot calculate quickly and accurately. In solving this problem, the authors use the black box testing method. Black box testing method is a test that sees the results of execution through test data and ensures the function of the software. Black box testing method has several testing techniques, namely Sample Testing, Boundary Value Analysis, Equivalence Partitions and others. From the testing techniques that have been mentioned, we use the Equivalence Partitions testing technique. Equivalence Partitions are tests that refer to data entry on the employee payroll application form, input will be tested and then put together based on the test function, both valid and invalid values. The expected results of this test are a payroll system for employees who are computerized, have standard rules in the process of developing the program so that it is easy to develop and maintain, and can minimize errors in processing salary calculations for employees.

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Modeling European hot spells using extreme value analysis

Climate Research ◽

10.3354/cr01191 ◽

2014 ◽

Vol 58 (3) ◽

pp. 193-207 ◽

Cited By ~ 13

Author(s):

C Photiadou ◽

MR Jones ◽

D Keellings ◽

CF Dewes

Keyword(s):

Extreme Value ◽

Extreme Value Analysis ◽

Value Analysis ◽

Hot Spells

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CONVEYOR MODEL AND IMPLEMENTATION OF THE REAL NUMBERS ADDER ON FPGA

ELECTRICAL AND COMPUTER SYSTEMS ◽

10.15276/eltecs.33.109.2020.3 ◽

2020 ◽

Vol 33 (109) ◽

pp. 21-31

Author(s):

І. Ya. Zeleneva ◽

Т. V. Golub ◽

T. S. Diachuk ◽

А. Ye. Didenko

Keyword(s):

Performance Improvement ◽

Experimental Studies ◽

Production Costs ◽

Floating Point ◽

Computing Device ◽

Quartus Ii ◽

Functional Blocks ◽

Mental Testing ◽

Processor Cores ◽

Floating Point Numbers

The purpose of these studies is to develop an effective structure and internal functional blocks of a digital computing device – an adder, that performs addition and subtraction operations on floating- point numbers presented in IEEE Std 754TM-2008 format. To improve the characteristics of the adder, the circuit uses conveying, that is, division into levels, each of which performs a specific action on numbers. This allows you to perform addition / subtraction operations on several numbers at the same time, which increas- es the performance of calculations, and also makes the adder suitable for use in modern synchronous cir- cuits. Each block of the conveyor structure of the adder on FPGA is synthesized as a separate project of a digital functional unit, and thus, the overall task is divided into separate subtasks, which facilitates experi- mental testing and phased debugging of the entire device. Experimental studies were performed using EDA Quartus II. The developed circuit was modeled on FPGAs of the Stratix III and Cyclone III family. An ana- logue of the developed circuit was a functionally similar device from Altera. A comparative analysis is made and reasoned conclusions are drawn that the performance improvement is achieved due to the conveyor structure of the adder. Implementation of arithmetic over the floating-point numbers on programmable logic integrated cir- cuits, in particular on FPGA, has such advantages as flexibility of use and low production costs, and also provides the opportunity to solve problems for which there are no ready-made solutions in the form of stand- ard devices presented on the market. The developed adder has a wide scope, since most modern computing devices need to process floating-point numbers. The proposed conveyor model of the adder is quite simple to implement on the FPGA and can be an alternative to using built-in multipliers and processor cores in cases where the complex functionality of these devices is redundant for a specific task.

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