Characterization of CNT interconnection bumps implemented for 1st level flip chip packaging

2011 ◽  
Author(s):  
Chin Chong Yap ◽  
Dunlin Tan ◽  
Christophe Brun ◽  
Edwin Hang Tong Teo ◽  
Jun Wei ◽  
...  
Keyword(s):  
Flip Chip ◽  
Flip Chip Packaging

Characterization of Moisture Induced Die Stresses in Flip Chip Packaging

2016 ◽  
Author(s):  
Quang Nguyen ◽  
Jordan C. Roberts ◽  
Jeffrey C. Suhling ◽  
Richard C. Jaeger ◽  
Pradeep Lall
Keyword(s):  
Flip Chip ◽  
Flip Chip Packaging

The Characterization of Underfill-Passivation Interface Under Monotonic and Fatigue Loading and Its Application to Flip Chip Reliability Prediction

2005 ◽  
Author(s):  
Saketh Mahalingam ◽  
Sandeep Tonapi ◽  
Suresh K. Sitaraman
Keyword(s):  
Reasonable Agreement ◽  
Flip Chip ◽  
Fatigue Loading ◽  
Reliability Prediction ◽  
Paris Law ◽  
Joint Reliability ◽  
Electrical Interconnection ◽  
Flip Chip Packaging ◽  
Underfill Material

Flip chip packaging technology is an attractive technique to achieve mechanical and electrical interconnection between the silicon chip and the substrate. Solder joint reliability in flip chip on organic board (FCOB) is enhanced by underfill application. The failure of solder joints in a flip chip package is usually associated with underfill delamination, esp. from the chip passivation. In this work, the fracture toughness of this interface is characterized for a novel no-flow underfill material using an innovative residual stress induced decohesion (RSID) test. Numerical modeling of the chip passivation-underfill interface indicates that the delamination will not progress under monotonic loading. However, the progress of delamination occurs under repeated thermal cycling. An empirical Paris law for underfill delamination has been developed and has been applied to predict delamination in actual flip chip packages. A reasonable agreement between the two is shown.

Thermal characterization of an epoxy-based underfill material for flip chip packaging

2000 ◽  
Vol 357-358 ◽  
pp. 1-8 ◽  
Author(s):  
Yi He ◽  
Brian E Moreira ◽  
Alan Overson ◽  
Stacy H Nakamura ◽  
Christine Bider ◽  
...  
Keyword(s):  
Flip Chip ◽  
Thermal Characterization ◽  
Flip Chip Packaging ◽  
Underfill Material

A High-Linearity 76–85-GHz 16-Element 8-Transmit/8-Receive Phased-Array Chip With High Isolation and Flip-Chip Packaging

2014 ◽  
Vol 62 (10) ◽  
pp. 2337-2356 ◽  
Author(s):  
Bon-Hyun Ku ◽  
Ozgur Inac ◽  
Michael Chang ◽  
Hyun-Ho Yang ◽  
Gabriel M. Rebeiz
Keyword(s):  
Flip Chip ◽  
Phased Array ◽  
High Isolation ◽  
High Linearity ◽  
Flip Chip Packaging

The Study of Underfill Epoxy Hardness in Reducing Curing Process Time for Flip Chip Packaging

2011 ◽  
Vol 462-463 ◽  
pp. 1194-1199
Author(s):  
Zainudin Kornain ◽  
Azman Jalar ◽  
Rozaidi Rashid ◽  
Shahrum Abdullah
Keyword(s):  
Thermal Expansion ◽  
Flip Chip ◽  
Ball Grid Array ◽  
Process Time ◽  
Curing Process ◽  
Curing Time ◽  
Hold Temperature ◽  
Flip Chip Packaging ◽  
Time Cycle ◽  
The Impact

Underfilling is the vital process to reduce the impact of the thermal stress that results from the mismatch in the co-efficient of thermal expansion (CTE) between the silicon chip and the substrate in Flip Chip Packaging. This paper reported the pattern of underfill’s hardness during curing process for large die Ceramic Flip Chip Ball Grid Array (FC-CBGA). A commercial amine based underfill epoxy was dispensed into HiCTE FC-CBGA and cured in curing oven under a new method of two-step curing profile. Nano-identation test was employed to investigate the hardness of underfill epoxy during curing steps. The result has shown the almost similar hardness of fillet area and centre of the package after cured which presented uniformity of curing states. The total curing time/cycle in production was potentially reduced due to no significant different of hardness after 60 min and 120 min during the period of second hold temperature.

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