Latent gate oxide defects caused by CDM-ESD

1995 ◽  
Author(s):  
J.C. Reiner
Keyword(s):  
Gate Oxide ◽  
Oxide Defects

Octahedral-Structured Gigantic Precipitates as the Origin of Gate-Oxide Defects in Metal-Oxide-Semiconductor Large-Scale-Integrated Circuits

1996 ◽  
Vol 35 (Part 1, No. 2B) ◽  
pp. 812-817 ◽  
Author(s):  
Manabu Itsumi ◽  
Hideo Akiya ◽  
Takemi Ueki ◽  
Masato Tomita ◽  
Masataka Yamawaki
Keyword(s):  
Integrated Circuits ◽  
Metal Oxide ◽  
Large Scale ◽  
Gate Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Oxide Defects

The defect-centric perspective of device and circuit reliability—From gate oxide defects to circuits

2016 ◽  
Vol 125 ◽  
pp. 52-62 ◽  
Author(s):  
B. Kaczer ◽  
J. Franco ◽  
P. Weckx ◽  
Ph.J. Roussel ◽  
M. Simicic ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Circuit Reliability ◽  
Oxide Defects

Effect of Negative Gate Bias on Single Pulse Avalanche Ruggedness of 1.2 kV Silicon Carbide MOSFETs

2018 ◽  
Vol 924 ◽  
pp. 735-738 ◽  
Author(s):  
Selamnesh Nida ◽  
Thomas Ziemann ◽  
Bhagyalakshmi Kakarla ◽  
Ulrike Grossner
Keyword(s):  
Silicon Carbide ◽  
Single Pulse ◽  
Gate Oxide ◽  
Gate Bias ◽  
Power Mosfets ◽  
Self Heating ◽  
Significant Difference ◽  
Oxide Defects ◽  
Voltage Spike ◽  
Avalanche Generation

When power MOSFETs experience a voltage spike initiating avalanche generation, a large amount of power is dissipated at the device junction. This leads to self-heating and lowers the threshold voltage. Some sources indicate that unintended opening of the channel creates a positive feedback, thereby increasing heat generation and leading to thermal runaway. Therefore, keeping MOSFETs off by applying a negative gate bias should improve avalanche ruggedness. In this report, this claim is investigated by comparing single pulse avalanche ruggedness of commercial 1.2 kV, 80 mΩ planar and trench MOSFETs at -10 V and 0 V off-state gate bias. Both planar and trench devices show a small increase in their breakdown voltage with negative gate bias. However, there is no significant difference in avalanche withstanding energy. Even in investigated trench gate devices where the gate oxide is susceptible to interface as well as oxide defects, keeping the gate voltage at VGS = -10 V did not result in improvements in ruggedness.

An Application of a Nanoprobe Technique in the Characterization of Advanced SRAM Devices

2008 ◽  
Author(s):  
Hung-Sung Lin ◽  
Chun-Ming Chen
Keyword(s):  
Barrier Layer ◽  
Gate Oxide ◽  
Active Area ◽  
Technology Node ◽  
Channel Gate ◽  
Oxide Defects ◽  
Contact Barrier

Abstract The importance of understanding mismatched behavior in SRAM devices has increased as the technology node has shrunk below 100nm. Using the nanoprobe technique [1-3], the MOS characteristics of failure bits in actual SRAM cells have been directly measured. After transistors that are failing were identified, the best approach for identifying nanoscale defects was determined. In this study, several types of nanoscale defects, such as offset spacer residue, salicide missing from the active area, doping missing from the channel, gate oxide defects, contact barrier layer residue, and severed poly-gate silicide were successfully discovered.

TEM Direct Observation of Gate Oxide Defects

2002 ◽  
Author(s):  
Nathan Wang ◽  
Sabbas Daniel
Keyword(s):  
Direct Observation ◽  
Three Dimensional ◽  
Final Analysis ◽  
Gate Oxide ◽  
Cross Sectional ◽  
Electrical Test ◽  
Wet Chemical ◽  
Oxide Defects ◽  
Oxide Damage

Abstract This paper describes the FA technique to identify very tiny defects that cause gate oxide damage. These defects as examples include crystal originated pits, gate oxide pinhole and residual. The defects may have the same electrical signature; the same kind of in gate oxide will be seen when the sample is simply deprocessed with wet chemical and observed with SEM; but they are distinctly different mechanisms. Electrical test, emission microscope, FIB and SEM were used to localize the defect and TEM for the final analysis. The application of planeview, cross-sectional and three-dimensional TEM is discussed.

scholarly journals Effect of Gate Oxide Defects on Tunnel Transistor RF Performance

2018 ◽  
Author(s):  
M. Hellenbrand ◽  
E. Memisevic ◽  
J. Svensson ◽  
A. Krishnaraja ◽  
E. Lind ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Oxide Defects ◽  
Tunnel Transistor ◽  
Rf Performance

Effect Of Layout On Gate Oxide Defects At Gate Edges

2005 ◽  
Author(s):  
Chun Jiang ◽  
D. Pramanik ◽  
C. Gabriel
Keyword(s):  
Gate Oxide ◽  
Oxide Defects
Sign in / Sign up

Export Citation Format

Share Document