scholarly journals Reducing the latency of L2 misses in shared-memory multiprocessors through on-chip directory integration

2003 ◽  
Author(s):  
M.E. Acacio ◽  
J. Gonzalez ◽  
J.M. Garcia ◽  
J. Duato
Keyword(s):  
Shared Memory ◽  
Shared Memory Multiprocessors ◽  
On Chip

scholarly journals ABOUT CACHE ASSOCIATIVITY IN LOW-COST SHARED MEMORY MULTI-MICROPROCESSORS

1995 ◽  
Vol 05 (03) ◽  
pp. 475-487
Author(s):  
N. DRACH ◽  
A. GEFFLAUT ◽  
P. JOUBERT ◽  
A. SEZNEC
Keyword(s):  
Shared Memory ◽  
Low Cost ◽  
The Other ◽  
Shared Memory Multiprocessors ◽  
Other Hand ◽  
Cache Associativity ◽  
Cache Organization ◽  
On Chip

Sizes of on-chip caches on current commercial microprocessors range from 16 Kbytes to 36 Kbytes. These microprocessors can be directly used in the design of a low cost single-bus shared memory multiprocessors without using any second-level cache. In this paper, we explore the viability of such a multi-microprocessor. Simulations results clearly establish that performance of such a system will be quite poor if on-chip caches are direct-mapped. On the other hand, when the on-chip caches are partially associative, the achieved level of performance is quite promising. In particular, two recently proposed innovative cache structures, the skewed-associative cache organization and the semi-unified cache organization are shown to work fine.

Benefits of cache-affinity scheduling in shared-memory multiprocessors

1993 ◽  
Vol 21 (1) ◽  
pp. 272-274 ◽  
Author(s):  
Josep Torrellas ◽  
Andrew Tucker ◽  
Anoop Gupta
Keyword(s):  
Shared Memory ◽  
Shared Memory Multiprocessors ◽  
Cache Affinity
Sign in / Sign up

Export Citation Format

Share Document