Effect of the lattice mismatch between copper thin-film interconnection and base material on the crystallinity of the interconnection

2012 ◽  
Author(s):  
Chuanhong Fan ◽  
Osamu Asai ◽  
Ken Suzuki ◽  
Hideo Miura
Keyword(s):  
Thin Film ◽  
Lattice Mismatch ◽  
Base Material ◽  
Copper Thin Film

Effect of the Lattice Mismatch Between Copper Thin-Film Interconnection and Base Material on the Crystallinity of the Interconnection

2013 ◽  
Author(s):  
Chuanhong Fan ◽  
Ryosuke Furuya ◽  
Osamu Asai ◽  
Ken Suzuki ◽  
Hideo Miura
Keyword(s):  
Thin Film ◽  
Seed Layer ◽  
Lattice Mismatch ◽  
Semiconductor Devices ◽  
Base Material ◽  
Diffraction Method ◽  
Copper Thin Film ◽  
New Material ◽  
Electroplated Copper ◽  
Electron Back Scattered Diffraction

In the present study, a new material, ruthenium whose lattice mismatch against copper is about 6%, was used as the seed layer of electroplated copper thin-film interconnections for semiconductor devices. The crystallinity of the copper thin-film interconnections was evaluated through an EBSD (Electron Back-scattered Diffraction) method and it is found that the crystallinity of them is improved drastically compared with those electroplated on the copper seed. The resistance and electro migration (EM) tolerance of the copper interconnections are also improved a lot compared with the interconnections electroplated on copper seed. Based on these results, a new guideline to design highly reliable electroplated copper thin-film interconnection has been established.

Crystallinity Control of Electroplated Interconnections for Improving Their Stability and Lifetime

2016 ◽  
Author(s):  
Jiatong Liu ◽  
Ken Suzuki ◽  
Hideo Miura
Keyword(s):  
Thin Film ◽  
Thin Films ◽  
Residual Stress ◽  
Grain Boundaries ◽  
Lattice Mismatch ◽  
Bulk Material ◽  
Chemical Properties ◽  
Mechanical Fracture ◽  
Copper Thin Film ◽  
Electroplated Copper

In a three-dimensional (3D) packaging systems, the interconnections which penetrate stacked silicon chips have been employed. Such interconnection structure is called TSV (Through Silicon Via) structure, and the via is recently filled by electroplated copper thin film. The electroplated copper thin films often consist of fine columnar grains and porous grain boundaries with high density of defects which don’t appear in conventional bulk material. This unique micro texture has been found to cause the wide variation of physical and chemical properties of this material. In the TSV structure, the shrinkage of the copper thin film caused by thermal deformation and recrystallization of the unique texture during high-temperature annealing is strictly constrained by surrounding rigid Si and thus, high tensile residual stress remains in the thin film after thermal annealing. High residual stress should give rise to mechanical fracture of the interconnections and the shift of electronic function of thin film devices formed in Si. Therefore, the residual stress in the interconnections should be minimized by controlling the appearance of the porous boundaries during electroplating for assuring the longterm reliability of the interconnections. As the lattice mismatch between Cu and its barrier film (Ta) is as larger as 18%, which is the main reason for the fine columnar structures and porous grain boundaries, it is necessary to control the underlayer crystallinity to improve the crystallinity of electroplated copper thin films. In this study, the effective method for controlling the crystallinity of the underlayer was investigated by improving the atomic configuration in the electroplated copper thin film. The result showed that by controlling the crystallinity of underlayer, crystallinity of electroplated copper thin films can be improved, the mechanical properties of thin films was improved and thus, stability and lifetime of electroplated copper interconnections can be improved.

Improvement of Thermal Conductivity of Electroplated Copper Interconnections by Controlling Their Crystallinity

2015 ◽  
Author(s):  
Masaru Gotoh ◽  
Ken Suzuki ◽  
Hideo Miura
Keyword(s):  
Thin Film ◽  
Thin Films ◽  
Thermal Conductivity ◽  
Thermal Properties ◽  
Grain Boundaries ◽  
Joule Heating ◽  
Seed Layer ◽  
Lattice Mismatch ◽  
Copper Thin Film ◽  
Electroplated Copper

Electroplated copper thin films are indispensable for the interconnections in the advanced electronic products, such as TSV (trough silicon via) structures, fine bumps, and thin-film interconnections in various devices and interposers. However, it has been reported that both electrical and mechanical properties of the films vary drastically comparing with those of conventional bulk copper. The main reason for the variation can be attributed to the fluctuation of the crystallinity of grains and grain boundaries in the films. Porous or sparse grain boundaries cause the increase in electrical resistivity and the embrittlement of the films. Thus, the thermal conductivity of the electroplated copper thin films should be varied drastically depending on their micro texture based on Wiedemann-Franz law. Since copper interconnections are used for not only electrical conductor but also thermal heat conductor, it is important to clarify the relationship between the crystallinity and thermal properties of the films. In this study, the local distributions of the crystallinity and physical properties were investigated experimentally. As the result of the temperature distribution due to local Joule heating along an interconnection, it was suggested that the variation in the quality of the grain boundaries in the electroplated copper thin-films caused the non-uniformity of the resistivity and thus, Joule heating in the thin films. In this study, the effect of the seed layer material on the thermal properties of the electroplated copper thin film was investigated. When a Ru seed layer was deposited as a buffer layer between the electroplated copper thin film and the Ta diffusion barrier layer, both the crystallinity and uniformity of grain boundaries in the electroplated copper films were improved since lattice mismatch between copper and the seed layer metal was decreased. The improvement of the crystallinity increased the long-term reliability of the interconnections under the loads of electromigration and stress-induced migration.

CVD copper thin film deposition using (α-methylstyrene)Cu(I)(hfac)

2001 ◽  
Vol 11 (PR3) ◽  
pp. Pr3-553-Pr3-560 ◽  
Author(s):  
W. Zhuang ◽  
L. J. Charneski ◽  
D. R. Evans ◽  
S. T. Hsu ◽  
Z. Tang ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Deposition ◽  
Film Deposition ◽  
Copper Thin Film

Environmental tests of embedded thin- and thick-film resistors in comparison to chip resistors

Circuit World ◽  
2014 ◽  
Vol 40 (1) ◽  
pp. 7-12 ◽  
Author(s):  
Wojciech Steplewski ◽  
Andrzej Dziedzic ◽  
Janusz Borecki ◽  
Grazyna Koziol ◽  
Tomasz Serzysko
Keyword(s):  
Thin Film ◽  
Thick Film ◽  
Electrical Resistance ◽  
Printed Circuit Boards ◽  
Base Material ◽  
Forming Process ◽  
Content Type ◽  
Thin Film Resistors ◽  
Embedded Resistors ◽  
The Impact

Purpose – The purpose of this paper is to investigate the influence of parameters of embedded resistive elements manufacturing process as well as the influence of environmental factors on their electrical resistance. The investigations were made in comparison to the similar constructions of discrete chip resistors assembled to standard printed circuit boards (PCBs). Design/methodology/approach – The investigations were based on the thin-film resistors made of NiP alloy, thick-film resistors made of carbon or carbon-silver inks as well as chip resistors in 0402 and 0603 packages. The polymer thick-film resistive films were screen-printed on the several types finishing materials of contact terminations such as copper, silver, and gold. To determine the sensitivity of embedded resistors versus standard assembled chip resistors on environmental exposure, the climatic chamber was used. The measurements of resistance were carried out periodically during the tests, and after the exposure cycles. Findings – The results show that the change of electrical resistance of embedded resistors, in dependence of construction and base material, is different and mainly not exceed the range of 3 per cent. The achieved results in reference to thin-film resistors are comparable with results for standard chip resistors. However, the results that were obtained for thick-film resistors with Ag and Ni/Au contacts are similar. It was not found the big differences between resistors with and without conformal coating. Research limitations/implications – The studies show that embedded resistors can be used interchangeably with chip resistors. It allows to save the area on the surface of PCB, occupied by these passive elements, for assembly of active elements (ICs) and thus enable to miniaturization of electronic devices. But embedding of passive elements into PCB requires to tackle the effect of each forming process steps on the operational properties. Originality/value – The technique of passive elements embedding into PCB is generally known; however, there are no detailed reports on the impact of individual process steps and environmental conditions on the stability of their electrical resistance. The studies allow to understand the importance of each factor process and the mechanisms of operational properties changes depending on the used materials.

Submerged Jet Impingement Cooling of a Nanostructured Plate

2010 ◽  
Author(s):  
Muhsincan Sesen ◽  
Ali Kosar ◽  
Ebru Demir ◽  
Evrim Kurtoglu ◽  
Nazli Kaplan ◽  
...  
Keyword(s):  
Thin Film ◽  
Heat Transfer ◽  
Heat Flux ◽  
Silicon Wafer ◽  
Heat Removal ◽  
Jet Impingement ◽  
Wafer Surface ◽  
Small Scale ◽  
Copper Thin Film ◽  
Thin Film Layer

In this paper, the results of a series of heat transfer experiments conducted on a compact electronics cooling device based on single phase jet impingement techniques are reported. Deionized-water is propelled into four microchannels of inner diameter 685 μm which are used as nozzles and located at a nozzle to surface distance of 2.5mm. The generated jet impingement is targeted through these channels towards the surface of a nanostructured plate. This plate of size 20mmx20mm consisted of ∼600 nm long copper nanorod arrays with an average nanorod diameter of ∼150 nm, which were integrated on top of a silicon wafer substrate coated with a copper thin film layer (i.e. Cu-nanorod/Cu-film/Silicon-wafer). Heat removal characteristics induced through jet impingement are investigated using the nanostructured plate and compared to results obtained from a flat plate of copper thin film coated on silicon wafer surface. Enhancement in heat transfer up to 15% using the nanostructured plate has been reported in this paper. Heat generated by small scale electronic devices is simulated using a thin film heater placed on an aluminum base. Surface temperatures are recorded by a data acquisition system with the thermocouples integrated on the surface at various locations. Constant heat flux provided by the film heater is delivered to the nanostructured plate placed on top of the base. Volumetric flow rate and heat flux values were varied in order to better characterize the potential enhancement in heat transfer by nanostructured surfaces.

Improvement of Thermal Conductivity of Electroplated Copper Thin-Film Interconnections by Controlling Their Micro Texture

2014 ◽  
Author(s):  
Pornvitoo Rittinon ◽  
Ken Suzuki ◽  
Hideo Miura
Keyword(s):  
Thin Film ◽  
Thin Films ◽  
Thermal Conductivity ◽  
Grain Boundaries ◽  
Diffraction Method ◽  
Electron Back Scatter Diffraction ◽  
High Resistivity ◽  
Copper Thin Film ◽  
Electroplated Copper ◽  
The Relationship

Copper thin films are indispensable for the interconnections in the advanced electronic products, such as TSV (Trough Silicon Via), fine bumps, and thin-film interconnections in various devices and interposers. However, it has been reported that both electrical and mechanical properties of the films vary drastically comparing with those of conventional bulk copper. The main reason for the variation can be attributed to the fluctuation of the crystallinity of grain boundaries in the films. Porous or sparse grain boundaries show very high resistivity and brittle fracture characteristic in the films. Thus, the thermal conductivity of the electroplated copper thin films should be varied drastically depending on their micro texture based on the Wiedemann-Franz’s law. Since the copper interconnections are used not only for the electrical conduction but also for the thermal conduction, it is very important to quantitatively evaluate the crystallinity of the polycrystalline thin-film materials and clarify the relationship between the crystallinity and thermal properties of the films. The crystallinity of the interconnections were quantitatively evaluated using an electron back-scatter diffraction method. It was found that the porous grain boundaries which contain a significant amount of vacancies increase the local electrical resistance in the interconnections, and thus, cause the local high Joule heating. Such porous grain boundaries can be eliminated by control the crystallinity of the seed layer material on which the electroplated copper thin film is electroplated.

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