A New Technique to Exploit Instruction-Level Parallelism for Reducing Microprocessor Power Consumption
Keyword(s):
2020 ◽
Vol 64
(3)
◽
pp. 207-211
Keyword(s):
Keyword(s):
Keyword(s):
2005 ◽
Vol 25
(1_suppl)
◽
pp. S543-S543