Modeling of IGBT-converters by interconnected subsystems with considering of snubber circuit and switching transistor time

2018 ◽  
Author(s):  
Michael V. Pronin ◽  
Alexey G. Vorontsov ◽  
Anait S. Grigoryan ◽  
Asan R. Mamutov ◽  
Irina A. Dikun
Keyword(s):  
Switching Transistor ◽  
Snubber Circuit

Model of Noise Source for HF Interference Calculation in a Converter Station

2007 ◽  
Vol 8 (6) ◽  
Author(s):  
Quanrui Hao ◽  
Zheng Xu
Keyword(s):  
Empirical Model ◽  
Noise Source ◽  
Equivalent Model ◽  
Basic Principles ◽  
Operating Modes ◽  
Snubber Circuit ◽  
Power Line Carrier ◽  
Actual Spectrum ◽  
Physical Quantities ◽  
Fft Analysis

For high-frequency (HF) interference in an HVDC converter station, the modeling of the noise source which causes interference with the power line carrier (PLC) remains a problem. Based on the profound analysis of the basic principles on which HF noise in PLC band is produced during the commutation process, the equivalent model of the HVDC valve with a snubber circuit is applied to the simulation of the GUI-GUANG HVDC project in PSCAD/EMTDC. Then spectrum plots of the noise source in the frequency domain are obtained by FFT analysis of the voltage waveforms gained from the simulation. Through analyzing the spectrum characteristics of the noise source in various operating modes, the main factors influencing the level of HF noise are found. Furthermore, a modified empirical model used to calculate the level of the noise source is introduced, with particular explanation of the physical quantities used in the model. The spectra of the noise source gained from the modified empirical model and from the simulation are compared with an actual spectrum based on the GUI-GUANG HVDC project. The results show that the modified empirical model can meet the requirement of HF interference calculation.

A new snubber circuit for high efficiency and overvoltage limitation in three-level GTO inverters

1997 ◽  
Vol 44 (2) ◽  
pp. 145-156 ◽  
Author(s):  
Jae-Hyeong Suh ◽  
Bum-Seok Suh ◽  
Dong-Seok Hyun
Keyword(s):  
High Efficiency ◽  
Snubber Circuit

Simulation of Modified Flyback Snubber Circuit for Isolated Bidirectional DC-DC Converter

2018 ◽  
Vol 19 (5) ◽  
Author(s):  
Kunalkumar Prakashbhai Bhatt ◽  
Ram Avtar Gupta ◽  
Nitin Gupta
Keyword(s):  
High Efficiency ◽  
Semiconductor Devices ◽  
Soft Switching ◽  
Leakage Inductance ◽  
Snubber Circuit ◽  
Mode Of Operation ◽  
Active Clamp ◽  
Semiconductor Switch ◽  
Effective Performance ◽  
Current Difference

Abstract Abstract: In this paper, a modified flyback snubber circuit for isolated bidirectional DC-DC converter has been introduced. The soft switching isolated snubber circuit provides an alternative path for the current difference created due to source inductance and leakage inductance. The auxiliary snubber circuit operates during the step-up conversion, and it only persists of the two semiconductor switch, two inductors one diode and two capacitors. Both semiconductor devices (G1, G2) of flyback snubber circuit achieve soft switching during turn ON and turn OFF condition. The PWM technique has been used to control the semiconductor devices. The different mode of operation has been discussed in detail. The effective performance of proposed converter system has been validated with the PSIM simulation tool. The proposed converter is compared with the active clamp converter based on efficiency. The loss comparison proves that flyback snubber circuit has high efficiency compared to active clamp converter.

scholarly journals A 2.5-GHz 1-V High Efficiency CMOS Power Amplifier IC with a Dual-Switching Transistor and Third Harmonic Tuning Technique

Electronics ◽  
2019 ◽  
Vol 8 (1) ◽  
pp. 69 ◽  
Author(s):  
Taufiq Alif Kurniawan ◽  
Toshihiko Yoshimasu
Keyword(s):  
Power Amplifier ◽  
High Efficiency ◽  
Low Voltage ◽  
Supply Voltage ◽  
Drain Current ◽  
Cmos Technology ◽  
Back Gate ◽  
Third Harmonic ◽  
Power Added Efficiency ◽  
Switching Transistor

This paper presents a 2.5-GHz low-voltage, high-efficiency CMOS power amplifier (PA) IC in 0.18-µm CMOS technology. The combination of a dual-switching transistor (DST) and a third harmonic tuning technique is proposed. The DST effectively improves the gain at the saturation power region when the additional gain extension of the secondary switching transistor compensates for the gain compression of the primary one. To achieve high-efficiency performance, the third harmonic tuning circuit is connected in parallel to the output load. Therefore, the flattened drain current and voltage waveforms are generated, which in turn reduce the overlapping and the dc power consumption significantly. In addition, a 0.5-V back-gate voltage is applied to the primary switching transistor to realize the low-voltage operation. At 1 V of supply voltage, the proposed PA has achieved a power added efficiency (PAE) of 34.5% and a saturated output power of 10.1 dBm.

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