Interconnect-aware design methodology for analog and mixed signal design in silicon based technologies using high bandwidth on-chip transmission lines

Author(s):  
D. Goren ◽  
M. Zelikson ◽  
R. Gordin
2017 ◽  
Vol 38 (6) ◽  
pp. 065004
Author(s):  
Hansheng Wang ◽  
Weiliang He ◽  
Minghui Zhang ◽  
Lu Tanh

2006 ◽  
Vol 94 (6) ◽  
pp. 1070-1088 ◽  
Author(s):  
J.M. Rabaey ◽  
F. De Bernardinis ◽  
A.M. Niknejad ◽  
B. Nikolic ◽  
A. Sangiovanni-Vincentelli

2007 ◽  
Vol 28 (11) ◽  
pp. 1025-1028 ◽  
Author(s):  
Fengyi Huang ◽  
Jingxue Lu ◽  
Yufeng Zhu ◽  
Nan Jiang ◽  
Xianchao Wang ◽  
...  

Author(s):  
Sowmya K. B. ◽  
Thanushree M.

As the technology grows, the tendency to increase the data rate also increases. Clocks with higher frequencies have to be generated to meet the increased data rate. Any mismatch between the clock rate and data rate will lead to the capture of the wrong data. Hence performing timing analysis for any design to validate the capture of correct data plays a major role in any System on chip. This paper explains the procedure followed to perform timing analysis for any mixed-signal design.


Author(s):  
J. Mondal ◽  
G. Raskin ◽  
C. Jackoski ◽  
J. Niehof ◽  
C. Munker ◽  
...  

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