A reply to "Comments on 'small geometry MOS Transistor capacitance measurement method using simple on-chip circuits'"

1985 ◽  
Vol 6 (1) ◽  
pp. 64-67 ◽  
Author(s):  
J.E. Orisian ◽  
H. Iwai ◽  
J.T. Walker ◽  
R.W. Dutton
Keyword(s):  
Measurement Method ◽  
Capacitance Measurement ◽  
Mos Transistor ◽  
On Chip

Small geometry MOS transistor capacitance measurement method using simple on-chip circuits

1984 ◽  
Vol 5 (10) ◽  
pp. 395-397 ◽  
Author(s):  
J. Oristian ◽  
H. Iwai ◽  
J. Walker ◽  
R. Dutton
Keyword(s):  
Measurement Method ◽  
Capacitance Measurement ◽  
Mos Transistor ◽  
On Chip

scholarly journals An Automatic Offset Calibration Method for Differential Charge-Based Capacitance Measurement

2021 ◽  
Vol 11 (2) ◽  
pp. 22
Author(s):  
Umberto Ferlito ◽  
Alfio Dario Grasso ◽  
Michele Vaiana ◽  
Giuseppe Bruno
Keyword(s):  
Standard Deviation ◽  
Output Voltage ◽  
Process Variations ◽  
Calibration Method ◽  
Capacitance Measurement ◽  
Effective Technique ◽  
Fully Integrated ◽  
Front End ◽  
Novel Method ◽  
On Chip

Charge-Based Capacitance Measurement (CBCM) technique is a simple but effective technique for measuring capacitance values down to the attofarad level. However, when adopted for fully on-chip implementation, this technique suffers output offset caused by mismatches and process variations. This paper introduces a novel method that compensates the offset of a fully integrated differential CBCM electronic front-end. After a detailed theoretical analysis of the differential CBCM topology, we present and discuss a modified architecture that compensates mismatches and increases robustness against mismatches and process variations. The proposed circuit has been simulated using a standard 130-nm technology and shows a sensitivity of 1.3 mV/aF and a 20× reduction of the standard deviation of the differential output voltage as compared to the traditional solution.

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