Enhancing multimedia processing by wave-pipelining integer units and floating point units in whole

In developing cutting edge VLSI processors, parallelism is one of the most important global standard strategies to achieve power conscious high performance. These features are more critical for ubiquitous systems with great demands for multimedia mobile processing. Then, one of most important issues for ubiquitous systems is instruction scheduling, because floating point units indispensable for multimedia mobile applications take longer latency than integer units. Although software parallelism has been inevitable to fully utilize hardware parallelism between regular scalar units, it has been really awkward. Thus, we describe in this article a double scheme to achieve instruction scheduling free ILP (instruction level parallelism) and apply the double scheme to a ubiquitous processor HCgorilla we have so far developed. The double scheme is the multifunctionalization of scalar units and making a resultant multifunctional unit (MFU) wave-pipeline. The multifunctionalization frees the instruction scheduling, and the wave-pipelining recovers the reduction of clock speed to be caused by the scale up of a multifunctional circuit. HCgorilla built-in the waved MFU is promising for wide-range dynamic ILP at a rate higher than regular processors.

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Java floating-point

JavaTech, an Introduction to Scientific and Technical Computing with Java ◽

10.1017/cbo9780511615948.028 ◽

2005 ◽

pp. 693-696

Keyword(s):

Floating Point

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New floating point impedance simulation using operational amplifiers

IEE Proceedings G Circuits Devices and Systems ◽

10.1049/ip-g-2.1989.0027 ◽

1989 ◽

Vol 136 (3) ◽

pp. 155 ◽

Cited By ~ 1

Author(s):

T.S. Rathore ◽

V. Singh

Keyword(s):

Operational Amplifiers ◽

Floating Point

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CONVEYOR MODEL AND IMPLEMENTATION OF THE REAL NUMBERS ADDER ON FPGA

ELECTRICAL AND COMPUTER SYSTEMS ◽

10.15276/eltecs.33.109.2020.3 ◽

2020 ◽

Vol 33 (109) ◽

pp. 21-31

Author(s):

І. Ya. Zeleneva ◽

Т. V. Golub ◽

T. S. Diachuk ◽

А. Ye. Didenko

Keyword(s):

Performance Improvement ◽

Experimental Studies ◽

Production Costs ◽

Floating Point ◽

Computing Device ◽

Quartus Ii ◽

Functional Blocks ◽

Mental Testing ◽

Processor Cores ◽

Floating Point Numbers

The purpose of these studies is to develop an effective structure and internal functional blocks of a digital computing device – an adder, that performs addition and subtraction operations on floating- point numbers presented in IEEE Std 754TM-2008 format. To improve the characteristics of the adder, the circuit uses conveying, that is, division into levels, each of which performs a specific action on numbers. This allows you to perform addition / subtraction operations on several numbers at the same time, which increas- es the performance of calculations, and also makes the adder suitable for use in modern synchronous cir- cuits. Each block of the conveyor structure of the adder on FPGA is synthesized as a separate project of a digital functional unit, and thus, the overall task is divided into separate subtasks, which facilitates experi- mental testing and phased debugging of the entire device. Experimental studies were performed using EDA Quartus II. The developed circuit was modeled on FPGAs of the Stratix III and Cyclone III family. An ana- logue of the developed circuit was a functionally similar device from Altera. A comparative analysis is made and reasoned conclusions are drawn that the performance improvement is achieved due to the conveyor structure of the adder. Implementation of arithmetic over the floating-point numbers on programmable logic integrated cir- cuits, in particular on FPGA, has such advantages as flexibility of use and low production costs, and also provides the opportunity to solve problems for which there are no ready-made solutions in the form of stand- ard devices presented on the market. The developed adder has a wide scope, since most modern computing devices need to process floating-point numbers. The proposed conveyor model of the adder is quite simple to implement on the FPGA and can be an alternative to using built-in multipliers and processor cores in cases where the complex functionality of these devices is redundant for a specific task.

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