Low-Cost Non-TSV Based 3D Packaging Using Glass Panel Embedding (GPE) for Power-Efficient, High-Bandwidth Heterogeneous Integration

2019 ◽  
Author(s):  
Siddharth Ravichandran ◽  
Shuhei Yamada ◽  
Fuhan Liu ◽  
Vanessa Smet ◽  
Mohanalingam Kathaperumal ◽  
...  
Keyword(s):  
Low Cost ◽  
Heterogeneous Integration ◽  
Glass Panel ◽  
Power Efficient ◽  
3D Packaging ◽  
High Bandwidth

scholarly journals Design and Demonstration of Glass Panel Embedding for 3D System Packages for Heterogeneous Integration Applications

2019 ◽  
Vol 16 (3) ◽  
pp. 124-135 ◽  
Author(s):  
Siddharth Ravichandran ◽  
Shuhei Yamada ◽  
Tomonori Ogawa ◽  
Tailong Shi ◽  
Fuhan Liu ◽  
...  
Keyword(s):  
Form Factor ◽  
High Performance ◽  
Coefficient Of Thermal Expansion ◽  
Large Body ◽  
Electrical Performance ◽  
Heterogeneous Integration ◽  
Wafer Level ◽  
Glass Panel ◽  
Packaging Technology ◽  
3D Packaging

Abstract This article demonstrates a next-generation high-performance 3D packaging technology with smaller form factor, excellent electrical performance, and reliability for heterogeneous integration. High-density logic-memory integration, today, is built predominantly using interposers which are fundamentally limited in assembly pitch and interconnect lengths, and they also are expensive as the package sizes increase. On the other hand, high-frequency applications continue to use laminates which are also limited by package size and ability to integrate many components. Wafer-level fan-out (WLFO) packaging promises better performance and form factor at lower costs, but current WLFO packages are mold-based and hence are limited to small packages. This article presents a 3D packaging technology using glass panel embedding (GPE) for high-performance with potential for large body size heterogeneous integration applications. The tailorable coefficient of thermal expansion of glass allows a reliable direct board attach of large GPE packages that not only benefits the form factor and signal speed but also provides radical benefits to power delivery. Unlike interposers and silicon bridges, GPE packages are not bump-limited and can support I/O densities comparable with backend-of-line with silicon-like redistribution wiring at much lower costs. The fundamental limitations such as die shift and poor dimensional stability of current organic WLFO packages are addressed by parametric process improvements to reduce die shift to <2 μm while also improving the RDL surface planarity for high-yielding fine-line structures and integrating through glass via (TGV) in the fan-out region for 3D packaging. This article describes the fabrication process for 3D GPE, leading to demonstration of a technology using embedding of chips with all-Cu interconnections at 40-μm I/O pitch with TGVs at 300-μm pitch, thus enabling double-side RDL and assembly of chips to achieve three levels of device integration.

Design and demonstration of Glass Panel Embedding for 3D System Packages for heterogeneous integration applications

2018 ◽  
Vol 2018 (1) ◽  
pp. 000331-000336 ◽  
Author(s):  
Siddharth Ravichandran ◽  
Shuhei Yamada ◽  
Tomonori Ogawa ◽  
Tailong Shi ◽  
Fuhan Liu ◽  
...  
Keyword(s):  
Form Factor ◽  
High Performance ◽  
Power Delivery ◽  
Electrical Performance ◽  
Heterogeneous Integration ◽  
Glass Panel ◽  
Process Improvements ◽  
Fundamental Limitations ◽  
Device Integration ◽  
3D Packaging

Abstract This paper demonstrates a next generation high-performance 3D packaging architecture with smaller form factor, excellent electrical performance and reliability for heterogeneous integration. High density Logic-HBM integration, today, is built predominantly using interposers which are fundamentally limited in assembly pitch and interconnect lengths, and they also are expensive as the package sizes increase. On the other hand, high-frequency applications continue to use laminates which are again limited by package size and ability to integrate many components. WLFO promises better performance and form factor at lower costs, but current WLFO packages are mold-based and hence are limited to small packages. This paper presents the first demonstration of 3D Glass Panel Embedding (GPE) technology for high-performance large package applications involving heterogeneous integration. The tailorable CTE of glass allows a reliable direct board SMT of large GPE packages that not only benefits form factor and signal speed, but also provides radical benefits to power delivery. Unlike interposers and silicon bridges, GPE packages are not bump limited and can support BEOL-like I/O densities with Silicon-like RDL at much lower costs. The fundamental limitations like die-shift and poor dimensional stability of current organic WLFO packages are addressed by parametric process improvements to reduce die-shift to <2 um while also improving the RDL surface planarity for high-yielding fine-line structures. This paper describes the fabrication process for 3D GPE, leading to demonstration of a technology using embedding of chips with all-Cu interconnections at 40um I/O pitch while also enabling double-side assembly of chips to achieve 3 levels of device integration.

Low-Cost Heat Insulating Film Design for BIPV Modules Based on Multi-Layer Inorganic Materials

2012 ◽  
Vol 452-453 ◽  
pp. 1424-1428
Author(s):  
Han Min Tian ◽  
Li Jia Guo ◽  
Wen Feng Duan ◽  
Rui Xia Yang ◽  
Feng Lan Tian
Keyword(s):  
Refractive Index ◽  
Visible Light ◽  
Absorption Rate ◽  
Heat Insulation ◽  
Low Cost ◽  
Heat Rate ◽  
Optimum Combination ◽  
Inorganic Materials ◽  
Tempered Glass ◽  
Glass Panel

By analyzing the transmitionce and heat rate of insulating antireflection films conposed by refractive-index adjustable SiO2 layer and TiO2 layers, the optimum combination of antireflection films of BIPV is obtained. The absorption rate at the ultraviolet part that wavelenght excessive inadequate 400nm of the optimized fils is 99.9%, which are directly designed on the surface of the low iron tempered glass panel of BIPV, and in the wavelength range 400nm-800nm, the visible light transmitionce rate is up to 99.5%, and the heat that wavelenght excessive 800nm is reflected of 20%. For the multilayer heat insulation films are composed with the same kind of material while with different refractive indexes, there is no projecting stress between these films and no constraints during the production process of different films for the possible low cost heat insulating of BIPV.

scholarly journals Thermal Modulation of a High-Bandwidth Gas Sensor Array in Real-Time for Application on a Mobile Robot

Proceedings ◽  
2018 ◽  
Vol 2 (13) ◽  
pp. 858 ◽  
Author(s):  
Timothy A. Vincent ◽  
Yuxin Xing ◽  
Marina Cole ◽  
Julian W. Gardner
Keyword(s):  
Signal Processing ◽  
Mobile Robot ◽  
Real Time ◽  
Low Cost ◽  
Processing Technique ◽  
Signal Processing Technique ◽  
Baseline Drift ◽  
Gas Sensor Array ◽  
Sensor Module ◽  
High Bandwidth

A new signal processing technique has been developed for resistive metal oxide (MOX) gas sensors to enable high-bandwidth measurements and enhanced selectivity at PPM levels (<50 PPM VOCs). An embedded micro-heater is thermally pulsed from 225 to 350 °C, which enables the chemical reactions in the sensor film (e.g., SnO2, WO3, NiO) to be extracted using a fast Fourier transform. Signal processing is performed in real-time using a low-cost microcontroller integrated into a sensor module. The approach enables the remove of baseline drift and is resilient to environmental temperature changes. Bench-top experimental results are presented for 50 to 200 ppm of ethanol and CO, which demonstrate our sensor system can be used within a mobile robot.

Long distance and high bandwidth wireless link tests for a 39 GHz to 28 GHz 5G low-cost repeater

2018 ◽  
Author(s):  
Simone Maier ◽  
Heinz Schlesinger ◽  
Wolfgang Templ ◽  
Harish Viswanathan
Keyword(s):  
Low Cost ◽  
Wireless Link ◽  
Long Distance ◽  
High Bandwidth

scholarly journals Proficient Car Parking System Based on Cluster Head Routing Protocol Utilizing IEEE 802.15.4

2016 ◽  
Vol 12 (06) ◽  
pp. 58
Author(s):  
Razi Iqbal ◽  
Sharif Arif ◽  
H.H.R Sherazi
Keyword(s):  
Communication Technology ◽  
Routing Protocol ◽  
Ieee 802.15.4 ◽  
Low Cost ◽  
Cluster Head ◽  
Power Efficient ◽  
Proposed Model ◽  
Efficient Communication ◽  
Parking System ◽  
The Coordinator

The paper discusses a proposed model for car parking system based on cluster head routing protocol utilizing a low cost and power efficient communication technology, ZigBee (IEEE 802.15.4). The model is designed in a way that car parking is divided into different clusters and each cluster has a head which acts a messenger for transmitting information to other heads and the coordinator of the network. Each cluster head is a ZigBee Host (Router) which collects the information of car presence in the parking slot. This information is then passed to the coordinator of the network which is used to display the information of available parking slots in a specific car parking area. Since there is only one coordinator in the network, so heads can transmit information to the coordinator using multi-hop communication if direct communication is not possible. Several simulations were performed to gauge the efficiency of the proposed model, and results show that the proposed model is reliable in communication and efficient in its operation.

MicroISPs: providing convenient and low-cost high-bandwidth Internet access

2000 ◽  
Vol 33 (1-6) ◽  
pp. 789-802 ◽  
Author(s):  
José Brustoloni ◽  
Juan Garay
Keyword(s):  
Low Cost ◽  
Internet Access ◽  
High Bandwidth

Innovative 3D Structures Utilizing Wafer Level Fan-Out (WLFO) Technology

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001486-001519
Author(s):  
Curtis Zwenger ◽  
JinYoung Khim ◽  
YoonJoo Khim ◽  
SeWoong Cha ◽  
SeungJae Lee ◽  
...  
Keyword(s):  
Low Cost ◽  
Ease Of Use ◽  
Wafer Level ◽  
3D Structures ◽  
Wafer Level Packaging ◽  
Functional Convergence ◽  
3D Packaging ◽  
Improved Design ◽  
On Chip ◽  
Mobile Handset

The tremendous growth in the mobile handset, tablet, and networking markets has been fueled by consumer demand for increased mobility, functionality, and ease of use. This, in turn, has been driving an increase in functional convergence and 3D integration of IC devices, resulting in the need for more complex and sophisticated packaging techniques. A variety of advanced IC interconnect technologies are addressing this growing need, such as Thru Silicon Via (TSV), Chip-on Chip (CoC), and Package-on-Package (PoP). In particular, the emerging Wafer Level Fan-Out (WLFO) technology provides unique and innovative extensions into the 3D packaging realm. Wafer Level Fan-Out is a package technology designed to provide increased I/O density within a reduced footprint and profile for low density single & multi-die applications at a lower cost. The improved design capability of WLFO is due, in part, to the fine feature capabilities associated with wafer level packaging. This can allow much more aggressive design rules to be applied compared to competing laminate-based technologies. In addition, the unique characteristics of WLFO enable innovative 3D structures to be created that address the need for IC integration in emerging mobile and networking applications. This paper will review the development of WLFO and its extension into unique 3D structures. In addition, the advantages of these WLFO designs will be reviewed in comparison to current competing packaging technologies. Process & material characterization, design simulation, and reliability data will be presented to show how WLFO is poised to provide robust, reliable, and low cost 3D packaging solutions for advanced mobile and networking products.

Wafer Level Assembly Technique Development for Fine Pitch Flip Chip 3D Die-to-Wafer Integration

2010 ◽  
Vol 2010 (1) ◽  
pp. 000548-000553
Author(s):  
Zhaozhi Li ◽  
Brian J. Lewis ◽  
Paul N. Houston ◽  
Daniel F. Baldwin ◽  
Eugene A. Stout ◽  
...  
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Three Dimensional ◽  
Cost Effective ◽  
Market Demand ◽  
Wafer Level ◽  
Packaging Technology ◽  
Fine Pitch ◽  
3D Packaging ◽  
Assembly Technique

Three Dimensional (3D) Packaging has become an industry obsession as the market demand continues to grow toward higher packaging densities and smaller form factor. In the meanwhile, the 3D die-to-wafer (D2W) packaging structure is gaining popularity due to its high manufacturing throughput and low cost per package. In this paper, the development of the assembly process for a 3D die-to-wafer packaging technology, that leverages the wafer level assembly technique and flip chip process, is introduced. Research efforts were focused on the high-density flip chip wafer level assembly techniques, as well as the challenges, innovations and solutions associated with this type of 3D packaging technology. Processing challenges and innovations addressed include flip chip fluxing methods for very fine-pitch and small bump sizes; wafer level flip chip assembly program creation and yield improvements; and set up of the Pb-free reflow profile for the assembled wafer. 100% yield was achieved on the test vehicle wafer that has totally 1,876 flip chip dies assembled on it. This work has demonstrated that the flip chip 3D die-to-wafer packaging architecture can be processed with robust yield and high manufacturing throughput, and thus to be a cost effective, rapid time to market alternative to emerging 3D wafer level integration methodologies.

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