Nano-Scale Conductive Films with Low Temperature Sintering for High Performance Fine Pitch Interconnect

2007 ◽  
Author(s):  
Yi Li ◽  
Myung Jin Yim ◽  
Kyung Sik Moon ◽  
C.P. Wong
Keyword(s):  
Low Temperature ◽  
High Performance ◽  
Low Temperature Sintering ◽  
Conductive Films ◽  
Nano Scale ◽  
Fine Pitch

Advances in Fine Pitch Off-Chip Interconnections Through the Use of a Novel Surface Finish

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 001531-001563
Author(s):  
Arnd Kilian ◽  
Gustavo Ramos ◽  
Rick Nichols ◽  
Robin Taylor ◽  
Vanessa Smet ◽  
...  
Keyword(s):  
Low Temperature ◽  
Surface Finish ◽  
System Integration ◽  
High Performance ◽  
Semiconductor Industry ◽  
Electroless Nickel ◽  
Interfacial Stress ◽  
Copper Oxidation ◽  
Fine Pitch ◽  
Metallurgical Bond

One constant in electronic system integration is the continuous trend towards smaller devices with increased functionality, driven by emerging mobile and high-performance applications. This brings the need for higher bandwidth at lower power, translating into increased I/O density, to enable highly-integrated systems with form factor reduction. These requirements result in the necessity of interconnection pitch-scaling, below 30 μm in the near future, and substrates with high wiring densities, leading to routing with sub 5 μm L/S where standard surface finishes (ENIG, ENEPIG) are no longer applicable. Copper pillar with solder caps technology is currently the prevalent solution for off-chip interconnections at fine pitch, dominating the high performance and mobile market with pitches as low as 40 μm in production. However, this technology faces many fundamental limitations in pitch scaling below 30 μm, due to solder bridging, IMC-solder interfacial stress management, and poor power handling capability of solders. All-copper interconnections without solder are very sought after by the semiconductor industry and have been applied to 3D-IC stacking, however no cost effective, manufacturable and scalable solution has been proposed to date for HVM and application to non CTE matched package structures. The low temperature Cu-Cu interconnection technology without solder recently patented by Georgia Tech PRC is one of the most promising solutions to this problem. The main bottleneck of copper oxidation is dealt with by application of ENIG on the Cu bumps and pads, enabling formation of a reliable metallurgical bond by thermocompression bonding (TCB) at temperatures below 200°C, in air, with cycle-times compatible with HVM targets. However, to ensure a bump collapse of 3 μm to overcome non-coplanarities and warpage, a pressure of 300MPa is used in the Process-of-Record (PoR) conditions, limiting the scalability of this technology. This paper introduces a novel Electroless Palladium / Autocatalytic Gold (EPAG) surface finish process, to enable the next generation of high density substrates and interconnections. With circa 100nm-thin Pd and Au layers, the EPAG finish can be applied to fine L/S wiring, with no risk of bridging adjacent Cu traces, even with spacing below 5 μm. Further, the EPAG finish is compatible with current interconnection processes; such as wire bonding, and the Cu pillar and solder cap technology for fine-pitch applications. For further pitch reduction, the EPAG surface finish was coupled to GT PRC's low-temperature Cu-interconnections, in an effort to reduce the bonding load for enhanced manufacturability without degrading the metallurgical bond or reliability. This paper is the first demonstration of such interconnections. The effect of the surface finish thickness and composition on the bonding load, assembly yield, quality of the metallurgical bond was extensively evaluated based on analysis of the metal interface microstructures and the chemical composition of the joints. The current PoR using Electroless Nickel / Immersion Gold (ENIG) coated Cu pillars and pads was used as reference. A novel surface finish is introduced, which allows formation of Cu-Cu interconnections without solder at lower pressure, between a silicon die and glass, organic or silicon substrate at fine pitch, allowing the performance improvements demanded by the IC Packaging Industry.

scholarly journals The Effect of an Ag Nanofilm on Low-Temperature Cu/Ag-Ag/Cu Chip Bonding in Air

2021 ◽  
Vol 11 (20) ◽  
pp. 9444
Author(s):  
Yoonho Kim ◽  
Seungmin Park ◽  
Sarah Eunkyung Kim
Keyword(s):  
Low Temperature ◽  
High Performance ◽  
Bonding Process ◽  
Bonding Interface ◽  
Fine Pitch ◽  
Bonding Technology ◽  
Cu Bonding ◽  
Cu Oxidation ◽  
Pure Cu

Low-temperature Cu-Cu bonding technology plays a key role in high-density and high-performance 3D interconnects. Despite the advantages of good electrical and thermal conductivity and the potential for fine pitch patterns, Cu bonding is vulnerable to oxidation and the high temperature of the bonding process. In this study, chip-level Cu bonding using an Ag nanofilm at 150 °C and 180 °C was studied in air, and the effect of the Ag nanofilm was investigated. A 15-nm Ag nanofilm prevented Cu oxidation prior to the Cu bonding process in air. In the bonding process, Cu diffused rapidly to the bonding interface and pure Cu-Cu bonding occurred. However, some Ag was observed at the bonding interface due to the short bonding time of 30 min in the absence of annealing. The shear strength of the Cu/Ag-Ag/Cu bonding interface was measured to be about 23.27 MPa, with some Ag remaining at the interface. This study demonstrated the good bonding quality of Cu bonding using an Ag nanofilm at 150 °C.

Low temperature sintering of high performance KNN-based lead-free piezoelectric ceramic using BCBM frit as sintering aid

2013 ◽  
Vol 31 (1-2) ◽  
pp. 42-47 ◽  
Author(s):  
Yue-Ming Li ◽  
Zong-Yang Shen ◽  
Zu-Gui Xiao ◽  
Zhu-Mei Wang ◽  
Wen-Qin Luo ◽  
...  
Keyword(s):  
Low Temperature ◽  
Piezoelectric Ceramic ◽  
High Performance ◽  
Lead Free ◽  
Low Temperature Sintering ◽  
Sintering Aid

Nano-scale Conductive Films for High Performance Fine Pitch Interconnect

2007 ◽  
Vol 990 ◽  
Author(s):  
Yi Li ◽  
Myung Jin Yim ◽  
Kyung Sik Moon ◽  
ChingPing Wong
Keyword(s):  
High Performance ◽  
Electrical Conductance ◽  
Conductive Adhesives ◽  
Bonding Pressure ◽  
Nano Scale ◽  
Fine Pitch ◽  
Conductive Film ◽  
Joint Resistance ◽  
Conductive Fillers ◽  
Free Solder

ABSTRACTIn this paper, a novel nano-scale conductive film which combines the advantages of both traditional anisotropic conductive adhesives/films (ACAs/ACFs) and nonconductive adhesives/films (NCAs/NCFs) is introduced and developed for next generation high performance ultra-fine pitch packaging applications. This novel interconnect film possesses the properties of electrical conduction along the z-direction with relatively low bonding pressure (ACF-like) and the ultra-fine pitch (< 100 nm) capability (NCF-like). Unlike typical ACF which requires 1–5 vol% of conductive fillers, the novel nano-scale conductive film only needs less than 0.1 vol% conductive fillers to achieve good electrical conductance in the z direction. The nano-scale conductive film also allows a lower bonding pressure than NCF to achieve a much lower joint resistance (over two orders of magnitude lower than typical ACF joints) and higher current carrying capability. With low temperature sintering of nano-silver fillers, the joint resistance of the nano-scale conductive film could be as low as 10−5 Ohm, even lower than the NCF and lead-free solder joints. The reliability of the nano-scale conductive film after high temperature and humidity test (85°C/85%RH) was also improved compared to the NCF joints. As such, a high performance, fine pitch conductive film was developed.

Analysis of Microstructure of Steel-Slag Ceramic Tiles

2010 ◽  
Vol 168-170 ◽  
pp. 1690-1694 ◽  
Author(s):  
Li Hua Zhao ◽  
Pu Liu ◽  
Xian Bin Ai ◽  
Xin Lu ◽  
Hao Bai ◽  
...  
Keyword(s):  
Low Temperature ◽  
High Performance ◽  
Ceramic Industry ◽  
Raw Materials ◽  
Steel Slag ◽  
Low Temperature Sintering ◽  
Sintering Process ◽  
Ceramic Tiles ◽  
Analysis Methods ◽  
Metallurgy Industry

The utilization of steel slag as resource is very important in the circle economy of metallurgy industry. Because the composition of steel slag is similar to that of the raw materials of ceramic industry, the sintering process of ceramics with steel slag as one of the raw materials was studied, and the ceramic products of high performance were abstained. Based on the study above, the microstructure of slag ceramic and its effect on the performance of ceramic were studied combining the analysis methods of SEM, DTA and XRD and the software FactSage. It’s found that the diopside phase was formed in the sintering process, which has significant effects on low temperature sintering and ceramic strength improving. Simulation by software FactSage showed that the diopside phase appears when the content of the steel-slag reaches 25%, while the content of slag is higher there are more diopside phase generation.

Low-Temperature Sintering of Nanoscale Silver Pastes for High-Performance and Highly-Reliable Device Interconnection

2005 ◽  
Author(s):  
John G. Bai ◽  
Zach Z. Zhang ◽  
Jesus N. Calata ◽  
Guo-Quan Lu
Keyword(s):  
Low Temperature ◽  
High Performance ◽  
Semiconductor Device ◽  
Silver Powder ◽  
Effective Elastic Modulus ◽  
Low Temperature Sintering ◽  
Mechanical Agitation ◽  
Schottky Rectifiers ◽  
Voltage Drops ◽  
Direct Bond Copper

In this paper, we report our development on making of nanoscale silver pastes and their low-temperature sintering for semiconductor device interconnections. The nanoscale silver pastes were prepared by dispersing 30-nm silver powder under ultrasonic vibration and mechanical agitation in an organic vehicle. Sintering of the silver paste prints at 280°C for 10 minutes resulted in a density of ~80% in the air ambient. Some important properties of the low-temperature sintered silver include ~2.4 W/K-cm for thermal conductivity, ~3.8 × 10−6 Ω-cm for electrical resistivity, and ~9 GPa for the effective elastic modulus. SiC Schottky rectifiers attached to either silver- or gold-coated direct bond copper (DBC) substrates show low forward voltage drops. The silver joints do not contain large voids but rather uniformly distributed microscale pores. Die-shear tests showed that bonding strengths of the silver joints were around 21 MPa on the gold-coated DBC substrates and 38 MPa on the silver-coated DBC substrates, respectively. The latter is comparable to that of reflowed eutectic lead-tin solder joints. Based on the findings in this work, the low-temperature sintering of nanoscale silver pastes is promising to be a high performance and highly-reliable semiconductor device bonding solution for high power packages.

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