Differences in the sub-processes of ultra fine pitch stencil printing due to type-6 and type-7 Pb-free solder pastes used for flip chip

2004 ◽  
Author(s):  
G.J. Jackson ◽  
M.W. Hendriksen ◽  
R.K. Durairaj ◽  
N.N. Ekere ◽  
M.P.Y. Desmulliez ◽  
...  
Keyword(s):  
Flip Chip ◽  
Stencil Printing ◽  
Fine Pitch ◽  
Solder Pastes ◽  
Free Solder

Sub process challenges in ultra fine pitch stencil printing of type‐6 and type‐7 Pb‐free solder pastes for flip chip assembly applications

2005 ◽  
Vol 17 (1) ◽  
pp. 24-32 ◽  
Author(s):  
G.J. Jackson ◽  
M.W. Hendriksen ◽  
R.W. Kay ◽  
M. Desmulliez ◽  
R.K. Durairaj ◽  
...  
Keyword(s):  
Flip Chip ◽  
Stencil Printing ◽  
Fine Pitch ◽  
Solder Pastes ◽  
Flip Chip Assembly ◽  
Free Solder

A Study of the Aperture Filling Process in Solder Paste Stencil Printing

1999 ◽  
Author(s):  
Jianbiao Pan ◽  
Gregory L. Tonkay
Keyword(s):  
Flip Chip ◽  
Deposition Process ◽  
Area Ratio ◽  
Solder Paste ◽  
Stencil Printing ◽  
Printing Process ◽  
Surface Mount ◽  
Fine Pitch ◽  
Main Indicator ◽  
Advanced Packaging

Abstract Stencil printing has been the dominant method of solder deposition in surface mount assembly. With the development of advanced packaging technologies such as ball grid array (BGA) and flip chip on board (FCOB), stencil printing will continue to play an important role. However, the stencil printing process is not completely understood because 52–71 percent of fine and ultra-fine pitch surface mount assembly defects are printing process related (Clouthier, 1999). This paper proposes an analytical model of the solder paste deposition process during stencil printing. The model derives the relationship between the transfer ratio and the area ratio. The area ratio is recommended as a main indicator for determining the maximum stencil thickness. This model explains two experimental phenomena. One is that increasing stencil thickness does not necessarily lead to thicker deposits. The other is that perpendicular apertures print thicker than parallel apertures.

Control of Bump Morphology in Lead Free Solder Plating for Higher Density Packaging

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001643-001669
Author(s):  
Koji Tatsumi ◽  
Kyouhei Mineo ◽  
Takeshi Hatta ◽  
Takuma Katase ◽  
Masayuki Ishikawa ◽  
...  
Keyword(s):  
High Speed ◽  
Flip Chip ◽  
New Technologies ◽  
Short Circuit ◽  
Lead Free Solder ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Different Shapes ◽  
Free Solder ◽  
High Density Packaging

Solder bumping is one of the key technologies for flip chip connection. Flip chip connection has been moving forward to its further downsizing and higher integration with new technologies, such as Cu pillar, micro bump and Through Silicon Via (TSV). Unlike some methods like solder printing and ball mounting, electroplating is a very promising technology for upcoming finer bump formation. We have been developing SnAg plating chemical while taking technology progress and customers' needs into consideration at the same time. Today, we see more variety of requests including for high speed plating to increase the productivity and also for high density packaging such as narrowing the bump pitch itself and downsizing of the bump diameter. To meet these technical needs, some adjustments of plating chemical will be necessary. This time we developed new plating chemicals to correspond to bump miniaturization. For instance, our new SnAg chemical can control bump morphology while maintaining the high deposition speed. With our new plating chemicals, we can deposit mushroom bumps that grow vertically against the resist surface, also this new chemicals work effectively to prevent short-circuit between mushroom bumps with fine pitch from forming. In addition, we succeeded in developing high speed Cu pillar plating chemicals that can control the surface morphology to create different shapes. We'd like to present our updates on controlling bump morphology for various applications.

Thermally Activated Bumping Process using Sn3.0Ag0.5Cu Solder Powder for Low-Cost Interposers

2013 ◽  
Vol 2013 (1) ◽  
pp. 000420-000423
Author(s):  
Kwang-Seong Choi ◽  
Ho-Eun Bae ◽  
Haksun Lee ◽  
Hyun-Cheol Bae ◽  
Yong-Sung Eom
Keyword(s):  
Screen Printing ◽  
Flip Chip ◽  
Solder Bump ◽  
Low Cost ◽  
Organic Substrate ◽  
Lead Free ◽  
Lead Free Solder ◽  
Thermally Activated ◽  
Fine Pitch ◽  
Free Solder

A novel bumping process using solder bump maker (SBM) is developed for fine-pitch flip chip bonding. It features maskless screen printing process with the result that a fine-pitch, low-cost, and lead-free solder-on-pad (SoP) technology can be easily implemented. The process includes two main steps: one is the thermally activated aggregation of solder powder on the metal pads on a substrate and the other is the reflow of the deposited powder on the pads. Only a small quantity of solder powder adjacent to the pads can join the first step, so a quite uniform SoP array on the substrate can be easily obtained regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of 130 μm is, successfully, formed.

Developments in Stencil Printing Technology for 0.3mm Pitch CSP Assembly

2011 ◽  
Vol 2011 (1) ◽  
pp. 000502-000508 ◽  
Author(s):  
Mark Whitmore ◽  
Clive Ashmore
Keyword(s):  
Form Factor ◽  
Area Ratio ◽  
Transfer Efficiency ◽  
Solder Paste ◽  
Assembly Process ◽  
Next Generation ◽  
Stencil Printing ◽  
Printing Process ◽  
Fine Pitch ◽  
Solder Pastes

As electronics assemblies continue to shrink in form factor, forcing designers towards smaller components with decreasing pitches, the Surface Mount assembly process is becoming increasingly challenged. A new “active” squeegee printing process has been developed to assist in the stencil printing of solder pastes for next generation ultra fine pitch components such as 0.3mm pitch CSP’s. Results indicate that today’s accepted stencil area ratio rules, which govern solder paste transfer efficiency can be significantly pushed to extend stencil printing process capabilities to stencil apertures having area ratios as low as 0.4. Such a breakthrough will allow the printing of ultra fine pitch components and additionally will assist with heterogeneous assembly concerns, to satisfy up and coming mixed technology demands.

Analysis of Solder Paste Release in Fine Pitch Stencil Printing Processes

1999 ◽  
Vol 121 (3) ◽  
pp. 169-178 ◽  
Author(s):  
G. Rodriguez ◽  
D. F. Baldwin
Keyword(s):  
High Speed ◽  
Flip Chip ◽  
Imaging System ◽  
Main Process ◽  
Print Quality ◽  
Solder Paste ◽  
Release Process ◽  
Stencil Printing ◽  
Fine Pitch ◽  
Analytical Approaches

Advanced electronics packaging technologies such as chip scale packages, fine pitch ball grid arrays, and flip chip are pushing solder paste stencil printing to the limit. In order to achieve solder print deposits of the sizes required for emerging electronic packaging technology, a rigorous understanding of the process is required. This paper seeks to expand our understanding of the physical characteristics of stencil printing specifically focusing on the solder paste release process based on experimental and analytical approaches. First, designed experiments were conducted to identify the main process variables affecting final print quality. An in-situ measurement system using a high speed imaging system monitored the solder paste release process. Based on experimental observations, different modes of solder paste release and their corresponding mechanisms were identified. A model was developed to predict print quality for fine pitch applications. The proposed model was experimentally verified showing good agreement with measured values for fine pitch and very fine pitch printing. It was found that the cohesive and adhesive forces acting on the paste tend to govern the release process rather than the viscous and inertial forces.

Corrections to "Ultra-fine pitch stencil printing for a low cost and low temperature flip-chip assembly process"

2007 ◽  
Vol 30 (2) ◽  
pp. 359-359
Author(s):  
Robert W. Kay ◽  
Stoyan Stoyanov ◽  
Greg P. Glinski ◽  
Chris Bailey ◽  
Marc P. Y. Desmulliez
Keyword(s):  
Low Temperature ◽  
Flip Chip ◽  
Low Cost ◽  
Assembly Process ◽  
Stencil Printing ◽  
Fine Pitch ◽  
Flip Chip Assembly

CFD Analysis of Molten Solder Flow Behavior and Bridging Mechanism During Solder Bump Formation

2019 ◽  
Author(s):  
Risa Miyazawa ◽  
Keishi Okamoto ◽  
Hiroyuki Mori
Keyword(s):  
Flip Chip ◽  
Solder Bump ◽  
Cfd Simulation ◽  
Simulation Analysis ◽  
Flow Behavior ◽  
Molten Solder ◽  
Factors Affecting ◽  
Fine Pitch ◽  
Flow Motion ◽  
Free Solder

Abstract Technology of fine pitch interconnect with lead-free solder joint has been developed to enhance the performance of flip-chip high density packages. This study presents an investigation of solder bump forming behavior by means of CFD simulation analysis. The flow motion of molten solder is analyzed with 3D model we developed, and the simulation result is validated with the experiment. Moreover, the investigation of factors affecting solder bridging across adjacent pads is also performed. It is revealed that wettability between liquid solder and organic insulator, which is represented as contact angle in the calculation has large effect on the solder bridging phenomena. The simulation result suggests that worsening the wettability of the insulator can reduce the occurrence of bridging.

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