Bending and twisting of 96.5Sn3.5Ag and 97.5Pb2.5Sn solder interconnects with creep

2002 ◽  
Author(s):  
J.H. Lau
Keyword(s):  
Solder Interconnects

Case Studies of Brittle Interfacial Failures in Area Array Solder Interconnects

2000 ◽  
Author(s):  
George M. Wenger ◽  
Richard J. Coyle ◽  
Patrick P. Solan ◽  
John K. Dorey ◽  
Courtney V. Dodd ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Failure Modes ◽  
Electroless Nickel ◽  
Electrical Performance ◽  
Printed Wiring Board ◽  
Solder Interconnects ◽  
Area Array ◽  
Surface Finishes ◽  
Soldering Reaction

Abstract A common pad finish on area array (BGA or CSP) packages and printed wiring board (PWB) substrates is Ni/Au, using either electrolytic or electroless deposition processes. Although both Ni/Au processes provide flat, solderable surface finishes, there are an increasing number of applications of the electroless nickel/immersion gold (ENi/IAu) surface finish in response to requirements for increased density and electrical performance. This increasing usage continues despite mounting evidence that Ni/Au causes or contributes to catastrophic, brittle, interfacial solder joint fractures. These brittle, interfacial fractures occur early in service or can be generated under a variety of laboratory testing conditions including thermal cycling (premature failures), isothermal aging (high temperature storage), and mechanical testing. There are major initiatives by electronics industry consortia as well as research by individual companies to eliminate these fracture phenomena. Despite these efforts, interfacial fractures associated with Ni/Au surface finishes continue to be reported and specific failure mechanisms and root cause of these failures remains under investigation. Failure analysis techniques and methodologies are crucial to advancing the understanding of these phenomena. In this study, the scope of the fracture problem is illustrated using three failure analysis case studies of brittle interfacial fractures in area array solder interconnects. Two distinct failure modes are associated with Ni/Au surface finishes. In both modes, the fracture surfaces appear to be relatively flat with little evidence of plastic deformation. Detailed metallography, scanning electron microscopy (SEM), energy dispersive x-ray analysis (EDX), and an understanding of the metallurgy of the soldering reaction are required to avoid misinterpreting the failure modes.

Experimental Study of Void Formation in High-Lead Solder Joints of Flip-Chip Assemblies

2004 ◽  
Vol 127 (2) ◽  
pp. 120-126 ◽  
Author(s):  
Daijiao Wang ◽  
Ronald L. Panton
Keyword(s):  
Flip Chip ◽  
Solder Joints ◽  
Numerical Study ◽  
Void Formation ◽  
Middle Layer ◽  
Molten Solder ◽  
Previous Theory ◽  
Solder Interconnects ◽  
Heating Profiles ◽  
High Lead

Understanding the formation of voids in solder joints is important for predicting the long-term reliability of solder interconnects. This paper reports experimental research on the formation of void bubbles within molten solder bumps in flip-chip connections. For flip-chip-soldered electronic components, which have small solder volume, voids can be more detrimental to reliability. A previous theory based on thermocapillary flow reveals that the direction of heating influences void formation. Using different heating profiles, 480 solder joints of flip-chip assemblies were processed. A high-lead 90Pb∕8Sn∕2Ag solder was employed in the experiments. The solder samples were microsectioned to determine the actual size or diameter of the voids. A database on sizes and locations of voids was then constructed. More defective bumps, 80%, and higher void volume were found when the solder was melted from top (flip-chip side) to bottom (test board side). The observation on cases with melting direction from bottom to top had 40% defective bumps. The results show that a single big void is near the solder bump center with a few small voids near the edge. This supports the numerical study based on the thermocapillary theory. When the melting direction was reversed, many small voids appear near the edge. Big and middle-size voids tend to stay in the middle and outer regions from top towards middle layer of the bump. This experimental finding does not completely agree with the interpretation on the formation of voids by thermocapillary theory, however, the results do show that heat flux direction plays significant role in the formation and distribution of void bubbles in molten solder.

C4 EM and CPI Reliability Benefits and Process Challenges of FBEOL Integration Changes Implemented in Lead-free C4 Products

2015 ◽  
Vol 2015 (1) ◽  
pp. 000787-000792
Author(s):  
E. Misra ◽  
T. Wassick ◽  
I. Melville ◽  
K. Tunga ◽  
D. Questad ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Flip Chip ◽  
Process Integration ◽  
Semiconductor Industry ◽  
Lead Free ◽  
Solder Interconnects ◽  
Design Changes ◽  
Modeling Data ◽  
Free Solder ◽  
Low K

The introduction of low-k & ultra-low-k dielectrics, lead-free (Pb-free) solder interconnects or C4's, and organic flip-chip laminates for integrated circuits have led to some major reliability challenges for the semiconductor industry. These include C4 electromigration (EM) and mechanical failures induced with-in the Si chip due to chip-package interactions (CPI). In 32nm technology, certain novel design changes were evaluated in the last Cu wiring level and the Far Back End of Line levels (FBEOL) to strategically re-distribute the current more uniformly through the Pb-free C4 bumps and therefore improve the C4 EM capabilities of the technology. FBEOL process integration changes, such as increasing the thickness of the hard dielectric (SiNx & SiOx) and reducing the final via diameter, were also evaluated for reducing the mechanical stresses in the weaker BEOL levels and mitigating potential risks for mechanical failures within the Si chip. The supporting white-bump, C4 EM and electrical/mechanical modeling data that demonstrates the benefits of the design and integration changes will be discussed in detail in the paper. Some of the key processing and integration challenges observed due to the design and process updates and the corresponding mitigation steps taken will also be discussed.

Impact of isothermal aging on fine pitch BGA packages with Sn-Ag-Cu solder interconnects

2010 ◽  
Vol 2010 (1) ◽  
pp. 000298-000305
Author(s):  
Tae-Kyu Lee ◽  
Weidong Xie ◽  
Thomas R. Bieler ◽  
Kuo-Chuan Liu ◽  
Jie Xue
Keyword(s):  
Thermal Cycling ◽  
Microstructure Evolution ◽  
Isothermal Aging ◽  
Substrate Surface ◽  
Solder Interconnects ◽  
Surface Finishes ◽  
Bga Packages ◽  
Fine Pitch ◽  
Solder Balls

The interaction between isothermal aging and long-term reliability of fine pitch ball grid array (BGA) packages with Sn-3.0Ag-0.5Cu (wt%) solder ball interconnects are investigated. In this study, 0.4mm fine pitch packages with 0.3mm diameter Sn-Ag-Cu solder balls are used. Two different die sizes and two different package substrate surface finishes are selected to compare the internal strain impact and alloy effect, especially the Ni effect during thermal cycling. To see the thermal impact on the thermal performance and long-term reliability, the samples are isothermally aged and thermal cycled from 0 to 100°C with a 10minute dwell time. Based on weibull plots for each aging condition, the lifetime of the package reduced approximately 44% with 150°C aging precondition. The microstructure evolution is observed during thermal aging and thermal cycling with different phase microstructure transformations between electrolytic Ni/Au and OSP surface finishes, focusing on the microstructure evolution near the package side interface. Different mechanisms after aging at various conditions are observed, and their impacts on the fatigue life of solder joints are discussed.

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