Analysis of a three phase five-level dual tapped inductor quasi impedance source-nested neutral point clamped converter

2017 ◽  
Author(s):  
Akinola A. Ajayi-Obe ◽  
Azeem Khan
Keyword(s):  
Neutral Point ◽  
Three Phase ◽  
Clamped Converter

scholarly journals a Three Phase Voltage Source Neutral-Point-Clamped Converter with Divided Capacitors.

1997 ◽  
Vol 117 (2) ◽  
pp. 196-203
Author(s):  
Noriaki Kamigaito ◽  
Yasumasa Kubota ◽  
Shigeo Masukawa ◽  
Shoji Iida
Keyword(s):  
Neutral Point ◽  
Voltage Source ◽  
Phase Voltage ◽  
Three Phase ◽  
Clamped Converter

A three-phase voltage-source neutral-point-clamped converter with divided capacitors

1997 ◽  
Vol 121 (2) ◽  
pp. 72-82
Author(s):  
Noriaki Kamigaito ◽  
Yasumasa Kubota ◽  
Shigeo Masukawa ◽  
Shoji Iida
Keyword(s):  
Neutral Point ◽  
Voltage Source ◽  
Phase Voltage ◽  
Three Phase ◽  
Clamped Converter

scholarly journals Analysis and performance evaluation of a three-phase sparse neutral point clamped converter for industrial variable speed drives

2021 ◽  
Author(s):  
Davide Cittanti ◽  
Mattia Guacci ◽  
Spasoje Mirić ◽  
Radu Bojoi ◽  
Johann Walter Kolar
Keyword(s):  
Degrees Of Freedom ◽  
Performance Comparison ◽  
Neutral Point ◽  
Modulation Scheme ◽  
Phase System ◽  
Variable Speed ◽  
Variable Speed Drives ◽  
Chip Area ◽  
Three Phase ◽  
Clamped Converter

Abstract This paper analyzes the operation and characterizes the performance of a three-phase three-level (3-L) Sparse Neutral Point Clamped converter (SNPCC) for industrial variable speed drives (VSDs). The operating principle of the SNPCC, which advantageously employs a lower number of power transistors than a conventional 3-L inverter, is described in detail, focusing on the AC-side differential-mode and common-mode voltage formation and on the DC-side mid-point current generation processes. The degrees of freedom in the SNPCC modulation scheme are defined and several switching sequences are investigated. Afterwards, the stresses on the active and passive components (e.g. semiconductor losses, machine phase current ripple, DC-link capacitor RMS current, etc.) are calculated by analytical and/or numerical means, enabling a straightforward performance comparison among the identified switching sequences. The most suited modulation strategy for VSD applications is then selected and a chip area sizing procedure, aimed at minimizing the total semiconductor chip size, is applied to a 800V 7.5kW three-phase system. The performance limits of the designed SNPCC are evaluated and finally compared to the ones of conventional 2-L and 3-L solutions, highlighting the promising cost/performance trade-off of the analyzed topology.

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