Implementation and evaluation of an inline network measurement algorithm and its application to TCP-based service

Author(s):  
T. Tsugawa ◽  
Go Hasegawa ◽  
M. Murata
2010 ◽  
Vol 159 ◽  
pp. 46-50
Author(s):  
Xin Hai Wang

Application Layer Multicast (ALM) is more flexible than that in IP layer and easy to optimize for specific applications, so the research on it has become a hotspot. Aiming at the problem of most ALM protocol ignoring bandwidth of covering tree, the paper presented a new heuristic algorithm Max-Delta, which inferred the underlying link topology using end-to-end measurement technology. On the basis of this, a kind of Fast Application layer Tree (FAT) algorithm to construct covering tree was proposed to meet the requirements of bandwidth. In addition, the algorithm's time complexity was also analyzed. Simulation results show that Max-Delta algorithm can obtain network topology accurately with less network measurement times comparing with random measurement algorithm and longest path measurement algorithm.


2010 ◽  
Vol 30 (4) ◽  
pp. 888-891
Author(s):  
Tao GUO ◽  
Xu ZHOU ◽  
Zhi-ping WANG ◽  
Hui TANG
Keyword(s):  

2021 ◽  
Vol 194 ◽  
pp. 108155
Author(s):  
Rui Wang ◽  
Hongchao Du ◽  
Zhaoyan Shen ◽  
Zhiping Jia

Energies ◽  
2021 ◽  
Vol 14 (6) ◽  
pp. 1589
Author(s):  
Krzysztof Kołek ◽  
Andrzej Firlit ◽  
Krzysztof Piątek ◽  
Krzysztof Chmielowiec

Monitoring power quality (PQ) indicators is an important part of modern power grids’ maintenance. Among different PQ indicators, flicker severity coefficients Pst and Plt are measures of voltage fluctuations. In state-of-the-art PQ measuring devices, the flicker measurement channel is usually implemented as a dedicated processor subsystem. Implementation of the IEC 61000-4-15 compliant flicker measurement algorithm requires a significant amount of computational power. In typical PQ analysers, the flicker measurement is usually implemented as a part of the meter’s algorithm performed by the main processor. This paper considers the implementation of the flicker measurement as an FPGA module to offload the processor subsystem or operate as an IP core in FPGA-based system-on-chip units. The measurement algorithm is developed and validated as a Simulink diagram, which is then converted to a fixed-point representation. Parts of the diagram are applied for automatic VHDL code generation, and the classifier block is implemented as a local soft-processor system. A simple eight-bit processor operates within the flicker measurement coprocessor and performs statistical operations. Finally, an IP module is created that can be considered as a flicker coprocessor module. When using the coprocessor, the main processor’s only role is to trigger the coprocessor and read the results, while the coprocessor independently calculates the flicker coefficients.


Author(s):  
Shiping Li ◽  
Jingang Zhong ◽  
Weixin Ling ◽  
Rui Min ◽  
Zhuoming Chen ◽  
...  

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