A Cost Effective Centralized Adaptive Routing for Networks-on-Chip

2011 ◽  
Author(s):  
Ran Manevich ◽  
Israel Cidon ◽  
Avinoam Kolodny ◽  
Isask'har Walter ◽  
Shmuel Wimer
Keyword(s):  
Adaptive Routing ◽  
Cost Effective ◽  
Networks On Chip ◽  
On Chip

First-Last: A Cost-Effective Adaptive Routing Solution for TSV-Based Three-Dimensional Networks-on-Chip

2018 ◽  
Vol 67 (10) ◽  
pp. 1430-1444 ◽  
Author(s):  
Amir Charif ◽  
Alexandre Coelho ◽  
Masoumeh Ebrahimi ◽  
Nader Bagherzadeh ◽  
Nacer-Eddine Zergainoh
Keyword(s):  
Three Dimensional ◽  
Adaptive Routing ◽  
Cost Effective ◽  
Networks On Chip ◽  
On Chip

scholarly journals Exploring a New Adaptive Routing Based on the Dijkstra Algorithm in Optical Networks-on-Chip

Micromachines ◽  
2021 ◽  
Vol 12 (1) ◽  
pp. 54
Author(s):  
Yan-Li Zheng ◽  
Ting-Ting Song ◽  
Jun-Xiong Chai ◽  
Xiao-Ping Yang ◽  
Meng-Meng Yu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Power Control ◽  
Optical Networks ◽  
Output Power ◽  
Network Performance ◽  
Transmission Loss ◽  
Adaptive Routing ◽  
Dijkstra Algorithm ◽  
Networks On Chip ◽  
On Chip

The photoelectric hybrid network has been proposed to achieve the ultrahigh bandwidth, lower delay, and less power consumption for chip multiprocessor (CMP) systems. However, a large number of optical elements used in optical networks-on-chip (ONoCs) generate high transmission loss which will influence network performance severely and increase power consumption. In this paper, the Dijkstra algorithm is adopted to realize adaptive routing with minimum transmission loss of link and reduce the output power of the link transmitter in mesh-based ONoCs. The numerical simulation results demonstrate that the transmission loss of a link in optimized power control based on the Dijkstra algorithm could be maximally reduced compared with traditional power control based on the dimensional routing algorithm. Additionally, it has a greater advantage in saving the average output power of optical transmitter compared to the adaptive power control in previous studies, while the network size expands. With the aid of simulation software OPNET, the network performance simulations in an optimized network revealed that the end-to-end (ETE) latency and throughput are not vastly reduced in regard to a traditional network. Hence, the optimized power control proposed in this paper can greatly reduce the power consumption of s network without having a big impact on network performance.

Wearout and Variation Tolerant Source Synchronous Communication for GALS Network-on-Chip Design

2014 ◽  
pp. 399-419
Author(s):  
Alessandro Strano ◽  
Carles Hernández ◽  
Federico Silla ◽  
Davide Bertozzi
Keyword(s):  
Cost Effective ◽  
Internal Communication ◽  
Synchronous Communication ◽  
Chip Design ◽  
Networks On Chip ◽  
Switch Architecture ◽  
Network Operation ◽  
Placement And Routing ◽  
Delay Variations ◽  
On Chip

In the context of multi-IP chips making use of internal communication paths other than the traditional buses, source synchronous links for use in multi-synchronous Networks-on-Chip (NoCs) are becoming the most vulnerable points for correct network operation and therefore need to be safeguarded against intra-link delay variations and signal misalignments. The intricacy of matching link net attributes during placement and routing and the growing role of process parameter variations in nanoscale silicon technologies, as well as the deterioration due to the ageing of the chip, are the root causes for this. This chapter addresses the challenge of designing a timing variation and layout mismatch tolerant link for synchronizer-based GALS NoCs by implementing a self-calibration mechanism. A timing variation detector senses the misalignment, due to process variation and wearout, between data lines with themselves and with the transmitter clock routed with data in source synchronous links. Then, a suitable delayed replica of the transmitter clock is selected for safe sampling of misaligned data. This chapter proves the robustness of the link in isolation with respect to a detector-less link, also addressing integration issues with the downstream synchronizer and switch architecture, proving the benefits in a realistic experimental setting for cost-effective NoCs.

Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design

2011 ◽  
Vol 2 (4) ◽  
pp. 1-20
Author(s):  
Alessandro Strano ◽  
Carles Hernández ◽  
Federico Silla ◽  
Davide Bertozzi
Keyword(s):  
Cost Effective ◽  
Synchronous Communication ◽  
Chip Design ◽  
Networks On Chip ◽  
Switch Architecture ◽  
Network Operation ◽  
Placement And Routing ◽  
Misaligned Data ◽  
Delay Variations ◽  
On Chip

Source synchronous links for use in multi-synchronous networks-on-chip (NoCs) are becoming the most vulnerable points for correct network operation and must be safeguarded against intra-link delay variations and signal misalignments. The intricacy of matching link net attributes during placement and routing and the growing role of process parameter variations in nanoscale silicon technologies are the root causes for this. This article addresses the challenge of designing a process variation and layout mismatch tolerant link for synchronizer-based GALS NoCs by implementing a self-calibration mechanism. A variation detector senses the variability-induced misalignment between data lines with themselves and with the transmitter clock routed with data in source synchronous links. A suitable delayed replica of the transmitter clock is then selected for safe sampling of misaligned data. The manuscript proves robustness of the link in isolation with respect to a detector-less link, but also assesses integration issues with the downstream synchronizer and switch architecture, proving the benefits in a realistic experimental setting for cost-effective NoCs.

Sign in / Sign up

Export Citation Format

Share Document