Source-Level Estimation of Energy Consumption and Execution Time of Embedded Software

2008 ◽  
Author(s):  
Carlo Brandolese
Keyword(s):  
Energy Consumption ◽  
Execution Time ◽  
Embedded Software ◽  
Source Level

Joint Optimization Offloading Strategy of Execution Time and Energy Consumption of Mobile Edge Computing

2021 ◽  
Vol 18 (5) ◽  
Author(s):  
Qingzhu Wang ◽  
Xiaoyun Cui
Keyword(s):  
Energy Consumption ◽  
Mobile Devices ◽  
Execution Time ◽  
Optimal Solution ◽  
Computation Offloading ◽  
Joint Optimization ◽  
Random Strategy ◽  
Fitness Value ◽  
Cloud Server ◽  
Time And Energy

As mobile devices become more and more powerful, applications generate a large number of computing tasks, and mobile devices themselves cannot meet the needs of users. This article proposes a computation offloading model in which execution units including mobile devices, edge server, and cloud server. Previous studies on joint optimization only considered tasks execution time and the energy consumption of mobile devices, and ignored the energy consumption of edge and cloud server. However, edge server and cloud server energy consumption have a significant impact on the final offloading decision. This paper comprehensively considers execution time and energy consumption of three execution units, and formulates task offloading decision as a single-objective optimization problem. Genetic algorithm with elitism preservation and random strategy is adopted to obtain optimal solution of the problem. At last, simulation experiments show that the proposed computation offloading model has lower fitness value compared with other computation offloading models.

Research on Network-on-Chip Dynamic and Adaptive Algorithm and Choice Strategy

2014 ◽  
Vol 539 ◽  
pp. 296-302
Author(s):  
Dong Li
Keyword(s):  
Energy Consumption ◽  
Execution Time ◽  
Adaptive Algorithm ◽  
Network On Chip ◽  
Time Dimension ◽  
Choice Strategy ◽  
Bus Structure ◽  
On Chip ◽  
Mapping Scheme ◽  
Single Objective

With further increase of the number of on-chip device, the bus structure has not met the requirements. In order to make better communication between each part, the chip designers need to explore a new structure to solve the interconnection of on-chip device. The paper proposes a network-on-chip dynamic and adaptive algorithm which selects NoC platform with 2-dimension mesh as the carrier, incorporates communication energy consumption and delay into unified cost function and uses ant colony optimization to realize NOC map facing energy consumption and delay. The experiment indicates that compared with random map, single objective optimization can separately saves (30%~47 %) and ( 20%~39%) in communication energy consumption and execution time compared with random map, and joint objective optimization can further excavate the potential of time dimension in mapping scheme dominated by the energy.

Abstract and Concrete Data Type Optimizations at the UML and C/C++ Level for Dynamic Embedded Software

2010 ◽  
pp. 55-83
Author(s):  
Christos Baloukas ◽  
Marijn Temmerman ◽  
Anne Keller ◽  
Stylianos Mamagkakis ◽  
Francky Catthoor ◽  
...  
Keyword(s):  
Energy Consumption ◽  
Embedded System ◽  
High Performance ◽  
Real Life ◽  
Holistic Approach ◽  
Embedded Software ◽  
Data Types ◽  
Design Engineers ◽  
Implementation Level ◽  
Abstraction Levels

An embedded system is a special-purpose system that performs predefined tasks, usually with very specific requirements. Since the system is dedicated to a specific task, design engineers can optimize it by exploiting very specialized knowledge, deriving an optimally customized system. Low energy consumption and high performance are both valid optimization targets to increase the value and mobility of the final system. Traditionally, conceptual embedded software models are built irrespectively of the underlying hardware platform, whereas embedded-system specialists typically start their optimization crusade from the executable code. This practice results in suboptimal implementations on the embedded platform because at the source-code level not all the inefficiencies introduced at the modelling level can be removed. In this book chapter, we describe both novel UML transformations at the modelling level and C/C++ transformations at the software implementation level. The transformations at both design abstraction levels target the data types of dynamic embedded software applications and provide optimizations guided by the relevant cost factors. Using a real life case study, we show how our transformations result in significant improvement in memory footprint, performance and energy consumption with respect to the initial implementation. Moreover, thanks to our holistic approach, we are able to identify new and non-trivial solutions that could hardly be found with the traditional design methods.

scholarly journals Creating Customized CGRAs for Scientific Applications

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 445
Author(s):  
George Charitopoulos ◽  
Ioannis Papaefstathiou ◽  
Dionisios N. Pnevmatikatos
Keyword(s):  
Energy Consumption ◽  
Execution Time ◽  
Coarse Grain ◽  
Scientific Applications ◽  
Cell Array ◽  
Analysis Methods ◽  
Reconfigurable Arrays ◽  
Hardware Implementations ◽  
Application Analysis ◽  
Software Implementations

Executing complex scientific applications on Coarse Grain Reconfigurable Arrays (CGRAs) offers improvements in the execution time and/or energy consumption when compared to optimized software implementations or even fully customized hardware solutions. In this work, we explore the potential of application analysis methods in such customized hardware solutions. We offer analysis metrics from various scientific applications and tailor the results that are to be used by MC-Def, a novel Mixed-CGRA Definition Framework targeting a Mixed-CGRA architecture that leverages the advantages of CGRAs and those of FPGAs by utilizing a customized cell-array along, with a separate LUT array being used for adaptability. Additionally, we present the implementation results regarding the VHDL-created hardware implementations of our CGRA cell concerning various scientific applications.

Estimation of energy consumption and execution time in early phases of design lifecycle: an application to biomedical systems

2008 ◽  
Vol 44 (23) ◽  
pp. 1343 ◽  
Author(s):  
G. Callou ◽  
P. Maciel ◽  
E. Andrade ◽  
B. Nogueira ◽  
E. Tavares
Keyword(s):  
Energy Consumption ◽  
Execution Time ◽  
Biomedical Systems ◽  
Early Phases

Security Estimation in Wireless Sensor Network Simulator

2016 ◽  
Vol 25 (07) ◽  
pp. 1650067 ◽  
Author(s):  
Álvaro Díaz ◽  
Javier González-Bayon ◽  
Pablo Sánchez
Keyword(s):  
Execution Time ◽  
Low Cost ◽  
Time Estimation ◽  
Embedded Software ◽  
Security Protocol ◽  
Sensor Nodes ◽  
Wireless Sensor ◽  
Network Simulator ◽  
Sensitive Data ◽  
Security Levels

Sensor nodes are low-power and low-cost devices with the requirement of a long autonomous lifetime. Therefore, the nodes have to use the available power carefully and avoid expensive computations or radio transmissions. In addition, as some wireless sensor networks (WSNs) process sensitive data, selecting a security protocol is vital. Cryptographic methods used in WSNs should fulfill the constraints of sensor nodes and should be evaluated for their security and power consumption. WSN engineers use several metrics to obtain estimations prior to network deployment. These metrics are usually related to power and execution time estimation. However, security is a feature that cannot be estimated and it is either “active” or “inactive”, with no possibility of introducing intermediate security levels. This lack of flexibility is a disadvantage in real deployments where different operation modes with different security and power specifications are often needed. This paper proposes including a new security estimation metric in a previously proposed framework for WSN simulation and embedded software (SW) performance analysis. This metric is called Security Estimation Metric (SEM) and it provides information about the security encryption used in WSN transmissions. Results show that the metric improves flexibility, granularity and execution time compared to other cryptographic tests.

scholarly journals Exploring Direct Convolution Performance on the Gemmini Accelerator

2020 ◽  
Author(s):  
Caio Vieira ◽  
Arthur Lorenzon ◽  
Lucas Schnorr ◽  
Philippe Navaux ◽  
Antonio Carlos Beck
Keyword(s):  
Neural Network ◽  
Computer Vision ◽  
Energy Consumption ◽  
Convolutional Neural Network ◽  
Building Block ◽  
Execution Time ◽  
Performance Gap ◽  
Main Building ◽  
Time And Energy ◽  
Lower Frequencies

Convolutional Neural Network (CNN) algorithms are becoming a recurrent solution to solve Computer Vision related problems. These networks employ convolutions as main building block, which greatly impact their performance since convolution is a costly operation. Due to its importance in CNN algorithms, this work evaluates convolution performance in the Gemmini accelerator and compare it to a conventional lightlyand heavily-loaded desktop CPU in terms of execution time and energy consumption. We show that Gemmini can achieve lower execution time and energy consumption when compared to a CPU even for small convolutions, and this performance gap grows with convolution size. Furthermore, we analyze the minimum Gemmini required frequency to match the same CPU execution time, and show that Gemmini can achieve the same runtime while working in much lower frequencies.

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