Design of a High Performance Traffic Generator on Network Processor

Author(s):  
Gianni Antichi ◽  
Andrea Di Pietro ◽  
Domenico Ficara ◽  
Stefano Giordano ◽  
Gregorio Procissi ◽  
...  
Sensors ◽  
2020 ◽  
Vol 20 (15) ◽  
pp. 4123 ◽  
Author(s):  
Alexandru Lavric ◽  
Adrian I. Petrariu ◽  
Eugen Coca ◽  
Valentin Popa

The digital revolution has changed the way we implement and use connected devices and systems by offering Internet communication capabilities to simple objects around us. The growth of information technologies, together with the concept of the Internet of Things (IoT), exponentially amplified the connectivity capabilities of devices. Up to this moment, the Long Range (LoRa) communication technology has been regarded as the perfect candidate, created to solve the issues of the IoT concept, such as scalability and the possibility of integrating a large number of sensors. The goal of this paper is to present an analysis of the communication collisions that occur through the evaluation of performance level in various scenarios for the LoRa technology. The first part addresses an empirical evaluation and the second part presents the development and validation of a LoRa traffic generator. The findings suggest that even if the packet payload increases, the communication resistance to interferences is not drastically affected, as one may expect. These results are analyzed by using a novel Software Defined Radio (SDR) technology LoRa traffic generator, that ensures a high-performance level in terms of generating a large LoRa traffic volume. Despite the use of orthogonal variable spreading factor technique, within the same communication channel, the collisions between LoRa packets may dramatically decrease the communication performance level.


2004 ◽  
pp. 301-326
Author(s):  
Jian-Guo Chen ◽  
David Sonnier ◽  
Robert Muñoz ◽  
Vinoj Kumar ◽  
Ambalavanar Arulambalam

2005 ◽  
Vol 47 (3) ◽  
Author(s):  
Rainer Hagenau ◽  
Carsten Albrecht ◽  
Erik Maehle ◽  
Andreas C. Döring

SummuryParallel processing is well established in high-performance computing. Currently, network processors as new emerging, special-purpose processors are targeted at the exploitation of parallelism to meet the requirements in data-plane processing with wire-speed. The achievable level of parallelism is determined by decisions in the architecture design and by the characteristics of the data-plane applications executed. We discuss two basic approaches in parallel processing, namely pipelining and concurrency, which establish basic models for parallel network processor organization. The features and constraints of these models are studied. Using this background some existing network processor architectures are reviewed and characterized regarding their potential in parallel data-plane processing.


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