Error detection in signed digit arithmetic circuit with parity checker [adder example]

Regular clocking scheme based design of cost-efficient comparator in QCA

Indonesian Journal of Electrical Engineering and Computer Science ◽

10.11591/ijeecs.v21.i1.pp44-55 ◽

2021 ◽

Vol 21 (1) ◽

pp. 44

Author(s):

Jayanta Pal ◽

Mojtaba Noorallahzadeh ◽

Jyotirmoy Sil Sharma ◽

Dhrubajyoti Bhowmik ◽

Apu Kumar Saha ◽

...

Keyword(s):

Power Dissipation ◽

Cost Efficiency ◽

Cmos Technology ◽

Processing Unit ◽

Arithmetic Circuit ◽

Quantum Dot Cellular Automata ◽

Central Processing ◽

Parity Checker ◽

Cost Efficient ◽

Scale Design

<span>Quantum-dot cellular automata (QCA) gained a notable attraction in the emerging nanotechnology to get the better of power consumption, density, nano-scale design, the performance of the present CMOS technology. Many designs had been proposed in QCA for an arithmetic circuit like adder, divider, parity checker and comparator etc. Most of the designs have been facing the challenges of cost efficiency, power dissi-pation, device density etc. However, consideration of design automation, underlying clocking layout and integration of the sub modules are the most important which has a direct impact on the fabrication of the design. This work proposed a novel cost ef-fective and power aware comparator design, which is an essential segment in central processing unit (CPU). The noticeable novelty of the design was the use of underlying regular clocking scheme. A new scalable, regular clocking scheme has been utilized in the coplanar design of the comparator which enables regular or uniform cell layout of QCA circuit. It also exhibited the significant improvement over existing counterparts having irregular clocking in terms of area and latency. QCADesigner was used to test and verify the functionality of the circuit and by using QCAPro the power dissipation has been analyzed.</span>

Download Full-text

On-chip optical parity checker using silicon photonic integrated circuits

Nanophotonics ◽

10.1515/nanoph-2018-0140 ◽

2018 ◽

Vol 7 (12) ◽

pp. 1939-1948 ◽

Cited By ~ 4

Author(s):

Zilong Liu ◽

Xiaosuo Wu ◽

Huifu Xiao ◽

Xu Han ◽

Wenping Chen ◽

...

Keyword(s):

Error Detection ◽

High Speed ◽

Silicon On Insulator ◽

Oxide Semiconductor ◽

Ring Resonators ◽

Cmos Process ◽

Operation Speed ◽

Parity Checker ◽

Silicon Photonic ◽

Error Detection And Correction

AbstractThe optical parity checker plays an important role in error detection and correction for high-speed, large-capacity, complex digital optical communication networks, which can be employed to detect and correct the error bits by using a specific coding theory such as introducing error-detecting and correcting codes in communication channels. In this paper, we report an integrated silicon photonic circuit that is capable of implementing the parity checking for binary string with an arbitrary number of bits. The proposed parity checker consisting of parallel cascaded N micro-ring resonators (MRRs) is based on directed logic scheme, which means that the operands applied to MRRs to control the switching states of the MRRs are electrical signals, the operation signals are optical signals, and the final operation results are obtained at the output ports in the form of light. A 3-bit parity checker with an operation speed of 10 kbps, fabricated on a silicon-on-insulator (SOI) platform using a standard commercial complementary metal-oxide-semiconductor (CMOS) process, was experimentally and successfully demonstrated.

Download Full-text