Fast run-time fault location in dependable FPGA-based applications

2002 ◽  
Author(s):  
Wei-Je Huang ◽  
S. Mitra ◽  
E.J. McCluskey
Keyword(s):  
Fault Location ◽  
Run Time

Modeling of Air-gap Flux Inside of Generator for Fault Location

2012 ◽  
Vol 132 (10) ◽  
pp. 872-878
Author(s):  
Junya Matsuki ◽  
Hisao Taoka ◽  
Shoji Kawasaki ◽  
Yuki Nakajima ◽  
Masakazu Horime ◽  
...  
Keyword(s):  
Fault Location ◽  
Air Gap

Short-Circuit Fault Location Interval Recognition Criteria in Electrical System

2019 ◽  
Vol 11 ◽  
pp. 33-39
Author(s):  
Yury Ya. LYAMETS ◽  
◽  
Mikhail V. MARTYNOV ◽  
Alexander N. MASLOV ◽  
◽  
...  
Keyword(s):  
Fault Location ◽  
Short Circuit ◽  
Electrical System ◽  
Short Circuit Fault

FAULT LOCATION ESTIMATION SYSTEMS: A CRITICAL REVIEW

2017 ◽  
Vol 5 (3) ◽  
pp. 17
Author(s):  
SANAD A. AHMED ◽  
ATTIA MAHMOUD A. ◽  
HAMED NABIL M. ◽  
ABDELAZIZ ALMOATAZ Y. ◽  
◽  
...  
Keyword(s):  
Critical Review ◽  
Fault Location ◽  
Location Estimation

Compiler-Aided Run-Time Performance Speed-Up in Super-Scalar Processor

10.28945/3391 ◽  
2009 ◽  
Author(s):  
Moshe Pelleh
Keyword(s):  
Embedded Systems ◽  
Embedded System ◽  
General Purpose ◽  
Experimental Results ◽  
Medium Size ◽  
Organic System ◽  
Software Application ◽  
Organic Systems ◽  
Special Cases ◽  
Run Time

In our world, where most systems become embedded systems, the approach of designing embedded systems is still frequently similar to the approach of designing organic systems (or not embedded systems). An organic system, like a personal computer or a work station, must be able to run any task submitted to it at any time (with certain constrains depending on the machine). Consequently, it must have a sophisticated general purpose Operating System (OS) to schedule, dispatch, maintain and monitor the tasks and assist them in special cases (particularly communication and synchronization between them and with external devices). These OSs require an overhead on the memory, on the cache and on the run time. Moreover, generally they are task oriented rather than machine oriented; therefore the processor's throughput is penalized. On the other hand, an embedded system, like an Anti-lock Braking System (ABS), executes always the same software application. Frequently it is a small or medium size system, or made up of several such systems. Many small or medium size embedded systems, with limited number of tasks, can be scheduled by our proposed hardware architecture, based on the Motorola 500MHz MPC7410 processor, enhancing its throughput and avoiding the software OS overhead, complexity, maintenance and price. Encouraged by our experimental results, we shall develop a compiler to assist our method. In the meantime we will present here our proposal and the experimental results.

Advanced Scan Diagnosis Based Fault Isolation and Defect Identification for Yield Learning

2005 ◽  
Author(s):  
Chris Eddleman ◽  
Nagesh Tamarapalli ◽  
Wu-Tung Cheng
Keyword(s):  
Failure Analysis ◽  
Fault Location ◽  
Effective Means ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Yield Analysis ◽  
Isolation Techniques ◽  
Yield Learning ◽  
Time Required ◽  
Inspection Data

Abstract Yield analysis of sub-micron devices is an ever-increasing challenge. The difficulty is compounded by the lack of in-line inspection data as many companies adopt foundry or fab-less models for acquiring wafers. In this scenario, failure analysis is increasingly critical to help drive yields. Failure analysis is a process of fault isolation, or a method of isolating failures as precisely as possible followed by identification of a physical defect. As the number of transistors and metal layers increase, traditional fault isolation techniques are less successful at isolating a cause of failures. Costs are increasing due to the amount of time needed to locate the physical defect. One solution to the yield analysis problem is scan diagnosis based fault isolation. Previous scan diagnosis based techniques were limited with little information about the type of fault and confidence of diagnosis. With new scan diagnosis algorithms it is now possible to not only isolate, but to identify the type of fault as well as assigning a confidence ranking prior to any destructive analysis. This paper presents multiple case studies illustrating the application of scan diagnosis as an effective means to achieve yield enhancement. The advanced scan diagnostic tool used in this study provides information about the fault type as well as fault location. This information focuses failure analysis efforts toward a suspected defect, decreasing the cycle time required to determine root cause, as well as increasing the over all success rate.

Electronic Package Failure Analysis Using TDR

2000 ◽  
Author(s):  
Dima A. Smolyansky
Keyword(s):  
Failure Analysis ◽  
Fault Location ◽  
Measurement Accuracy ◽  
Time Domain Reflectometry ◽  
Acoustic Imaging ◽  
X Ray ◽  
Analysis Techniques ◽  
Bga Packages ◽  
Impedance Profile ◽  
Nature Of Time

Abstract The visual nature of Time Domain Reflectometry (TDR) makes it a very natural technology that can assist with fault location in BGA packages, which typically have complex interweaving layouts that make standard failure analysis techniques, such as acoustic imaging and X-ray, less effective and more difficult to utilize. This article discusses the use of TDR for package failure analysis work. It analyzes in detail the TDR impedance deconvolution algorithm as applicable to electronic packaging fault location work, focusing on the opportunities that impedance deconvolution and the resulting true impedance profile opens up for such work. The article examines the TDR measurement accuracy and the comparative package failure analysis, and presents three main considerations for package failure analysis. It also touches upon the goal and the task of the failure analysts and TDR's specific signatures for the open and short connections.

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