Error detection of arithmetic circuits using a residue checker with signed-digit number system

2002 ◽  
Author(s):  
Shugang Wei ◽  
Kensuke Shimizu
Keyword(s):  
Error Detection ◽  
Number System ◽  
Arithmetic Circuits ◽  
Digit Number

On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits

2020 ◽  
Vol 36 (1) ◽  
pp. 33-46
Author(s):  
B. Deveautour ◽  
A. Virazel ◽  
P. Girard ◽  
V. Gherman
Keyword(s):  
Error Detection ◽  
Arithmetic Circuits ◽  
Approximate Computing ◽  
Detection Scheme

Residue Checker with Signed-Digit Arithmetic for Error Detection of Arithmetic Circuits

2003 ◽  
Vol 12 (01) ◽  
pp. 41-53 ◽  
Author(s):  
Shugang Wei ◽  
Kensuke Shimizu
Keyword(s):  
Real Time ◽  
Error Detection ◽  
Binary Tree ◽  
Word Length ◽  
Arithmetic Circuits ◽  
Binary Number ◽  
Residue Number ◽  
Residue Arithmetic ◽  
Large Product ◽  
Binary Tree Structure

This paper presents a fast residue checker for the error detection of arithmetic circuits. The residue checker consists of a number of residue arithmetic circuits such as adders, multipliers and binary-to-residue converters based on radix-two signed-digit (SD) number arithmetic. The proposed modulo m (m = 2p ± 1) adder is designed with a p-digit SD adder, so that the modulo m addition time is independent of the word length of operands. The modulo m multiplier and binary-to-residue number converter are constructed with a binary tree structure of the modulo m SD adders. Thus, the modulo m multiplication is performed in a time proportional to log 2 p and an n-bit binary number is converted into a p-digit SD residue number, n ≫ p, in a time proportional to log 2(n/p). By using the presented residue arithmetic circuits, the error detection can be performed in real-time for a large product-sum circuit.

scholarly journals DATA ERRORS CONTROL IN THE MODULAR NUMBER SYSTEM BASED ON THE NULLIFICATION PROCEDURE

2020 ◽  
pp. 237-246
Author(s):  
Victor Krasnobayev ◽  
Sergey Koshman ◽  
Sergey Moroz ◽  
Vyacheslav Kalashnikov ◽  
Vitaliy Kalashnikov
Keyword(s):  
Error Detection ◽  
Error Control ◽  
Number System ◽  
Practical Significance ◽  
Information Control ◽  
Detection Time ◽  
Data Errors ◽  
Pair Number ◽  
Residual Values ◽  
Correct Implementation

A method for error control in the modular number system (MNS) based on the use of the zeroing procedure is proposed. Error control in the MNS is a non-positional operation and requires the development of special methods, designed to increase the efficiency of this procedure. This method is designed to verify the correct implementation of the computing process of computer systems and components. It is assumed that the error in one module remainder does not affect the residual values corresponding to other modules (bases) of the MNS. The essence of the method of error control is to use the procedure of pair number zeroing with the preliminary fetching of digits. This makes it possible to increase the efficiency of information control, presented in the modular number system. The practical significance of the results obtained is that, in comparison with the existing methods of error control in MNS, the error detection time is more than halved.

scholarly journals On The Implementation of Densely Packed Decimal Number System Based Adder: Prospects and Challenges

2021 ◽  
Vol 25 (1) ◽  
pp. 20-30
Author(s):  
Srikant Kumar Beura ◽  
◽  
Rekib Uddin Ahmed ◽  
Bishnulatpam Pushpa Devi ◽  
Prabir Saha ◽  
...  
Keyword(s):  
Circuit Simulation ◽  
Number System ◽  
Decimal Digit ◽  
Performance Parameters ◽  
Design Technique ◽  
Digit Number ◽  
Time Saving ◽  
Decimal Number ◽  
Decimal Adder ◽  
Pros And Cons

Decimal digit number computation, through bit compression methodology, offers space and time saving, which can be incurred by the Chen-Ho and Densely Packed Decimal (DPD) coding techniques. Such coding techniques have a property of bit compression, like, three decimal digits can be represented by 10 bits instead of 12 bits in binary coded decimal (BCD) format. The compression has been obtained through the elimination of the redundant 0’s from BCD representation. This manuscript reports the pros and cons of the techniques mentioned above. The logic level functionalities have been examined through MATLAB, whereas circuit simulation has been erified through Cadence Spectre. Performance parameters (such as delay, power consumption) have been evaluated through CMOS gpdk45 nm technology. Furthermore, the best design has been chosen from them, and the decimal adder design technique has been incorporated in this paper.

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