Design rule centring for row redundant content addressable memories

2003 ◽  
Author(s):  
W.B. Noghani ◽  
I.P. Jalowiecki
Keyword(s):  
Design Rule ◽  
Content Addressable Memories

Failure Types & Analysis In Cu Process Development of Design-Rule 0.18μm CPU

2001 ◽  
Author(s):  
DongKwon Jeong ◽  
JuHyeon Ahn ◽  
SangIn Lee ◽  
JooHyuk Chung ◽  
ByungLyul Park ◽  
...  
Keyword(s):  
Process Improvement ◽  
Process Development ◽  
Metal Corrosion ◽  
Pass Rate ◽  
Design Rule ◽  
The Novel ◽  
Corrosion Loss ◽  
Barrier Metal ◽  
Development State ◽  
Failure Types

Abstract This paper presents the problems, the solutions, and the development state of the novel 0.18 μm Cu Metal Process through failure analysis of the Alpha CPU under development at Samsung Electronics. The presented problems include : “Via Bottom Lifting” induced by the Cu Via void, “Via Bottom dissociation” due to the IMD stress, “Via side dissociation” due to the poor formation of the Barrier Metal, “Via short/not-open failure” due to the IMD lifting, and Cu metal Corrosion/Loss. The analysis was carried out on the Via Contact Test Chain Patterns, using the “Electron (ION) Charge Up” method. After carefully analyzing each of the failure types, process improvement efforts followed. As a result, the pass rate of the via contact Rc was brought up from a mere 20% to 95%, and the device speed higher than 1.1 GHz was achieved, which surpasses the target speed of 1 GHz.

РАЗРАБОТКА ПРОТОТИПА ПРОГРАММНОГО МОДУЛЯ АВТОМАТИЗИРОВАННОЙ ГЕНЕРАЦИИ КВАЛИФИКАЦИОННЫХ ЯЧЕЕК ДЛЯ КОНТРОЛЯ ПРАВИЛ ПРОЕКТИРОВАНИЯ ИС

2020 ◽  
Vol 96 (3s) ◽  
pp. 721-725
Author(s):  
Ф.С. Золотухин ◽  
А.С. Надин ◽  
И.Е. Трифанихина
Keyword(s):  
Industrial Design ◽  
Automated Design ◽  
Design Rule ◽  
Software Module ◽  
The Real ◽  
Rule Checking ◽  
Design Rule Checking

Разработан прототип программного модуля генератора квалификационных ячеек для автоматизированного контроля геометрических правил проектирования DRC. Проведено тестирование прототипа генератора в реальных рабочих условиях проектирования. The paper presents a prototype of software module of the QA-cells Generator for automated Design Rule Checking. The QA-Cells Generator has been tested in the real workplace within actual microelectronic industrial design.

scholarly journals Efficient local locking for massively multithreaded in-memory hash-based operators

2021 ◽  
Author(s):  
Bashar Romanous ◽  
Skyler Windh ◽  
Ildar Absalyamov ◽  
Prerna Budhkar ◽  
Robert Halstead ◽  
...  
Keyword(s):  
Relational Databases ◽  
Aggregation Operators ◽  
Main Memory ◽  
Paradigm Shifts ◽  
Multithreaded Processors ◽  
Cache Hierarchies ◽  
Processor Architectures ◽  
Spatial Locality ◽  
Content Addressable Memories ◽  
Multi Core Processor

AbstractThe join and group-by aggregation are two memory intensive operators that are affecting the performance of relational databases. Hashing is a common approach used to implement both operators. Recent paradigm shifts in multi-core processor architectures have reinvigorated research into how the join and group-by aggregation operators can leverage these advances. However, the poor spatial locality of the hashing approach has hindered performance on multi-core processor architectures which rely on using large cache hierarchies for latency mitigation. Multithreaded architectures can better cope with poor spatial locality by masking memory latency with many outstanding requests. Nevertheless, the number of parallel threads, even in the most advanced multithreaded processors, such as UltraSPARC, is not enough to fully cover the main memory access latency. In this paper, we explore the hardware re-configurability of FPGAs to enable deeper execution pipelines that maintain hundreds (instead of tens) of outstanding memory requests across four FPGAs-drastically increasing concurrency and throughput. We present two end-to-end in-memory accelerators for the join and group-by aggregation operators using FPGAs. Both accelerators use massive multithreading to mask long memory delays of traversing linked-list data structures, while concurrently managing hundreds of thread states across four FPGAs locally. We explore how content addressable memories can be intermixed within our multithreaded designs to act as a synchronizing cache, which enforces locks and merges jobs together before they are written to memory. Throughput results for our hash-join operator accelerator show a speedup between 2$$\times $$ × and 3.4$$\times $$ × over the best multi-core approaches with comparable memory bandwidths on uniform and skewed datasets. The accelerator for the hash-based group-by aggregation operator demonstrates that leveraging CAMs achieves average speedup of 3.3$$\times $$ × with a best case of 9.4$$\times $$ × in terms of throughput over CPU implementations across five types of data distributions.

scholarly journals Scattering Analysis and Efficiency Optimization of Dielectric Pancharatnam–Berry-Phase Metasurfaces

Nanomaterials ◽  
2021 ◽  
Vol 11 (3) ◽  
pp. 586
Author(s):  
Chen-Yi Yu ◽  
Qiu-Chun Zeng ◽  
Chih-Jen Yu ◽  
Chien-Yuan Han ◽  
Chih-Ming Wang
Keyword(s):  
Phase Modulation ◽  
Rotation Angle ◽  
Berry Phase ◽  
Fine Tuning ◽  
Design Rule ◽  
Polarization Conversion ◽  
Swarm Optimization ◽  
Efficiency Optimization ◽  
Phase Type ◽  
Gradient Phase

In this study, the phase modulation ability of a dielectric Pancharatnam–Berry (PB) phase metasurface, consisting of nanofins, is theoretically analyzed. It is generally considered that the optical thickness of the unit cell of a PB-phase metasurface is λ/2, i.e., a half-waveplate for polarization conversion. It is found that the λ/2 is not essential for achieving a full 2π modulation. Nevertheless, a λ/2 thickness is still needed for a high polarization conversion efficiency. Moreover, a gradient phase metasurface is designed. With the help of the particle swarm optimization (PSO) method, the wavefront errors of the gradient phase metasurface are reduced by fine-tuning the rotation angle of the nanofins. The diffraction efficiency of the gradient phase metasurface is thus improved from 73.4% to 87.3%. This design rule can be utilized to optimize the efficiency of phase-type meta-devices, such as meta-deflectors and metalenses.

scholarly journals Design Rule Checking with a CNN Based Feature Extractor

2020 ◽  
Author(s):  
Luis Francisco ◽  
Tanmay Lagare ◽  
Arpit Jain ◽  
Somal Chaudhary ◽  
Madhura Kulkarni ◽  
...  
Keyword(s):  
Design Rule ◽  
Rule Checking ◽  
Feature Extractor ◽  
Design Rule Checking

P‐98: Digital Simulation and Design Rule for Avoiding Metal‐Reflection Mura in OLED FMLOC Products

2021 ◽  
Vol 52 (1) ◽  
pp. 1448-1451
Author(s):  
Xuefei Sun ◽  
Jaegeon You ◽  
Xinxing Wang ◽  
Liyan Liu ◽  
Yingtao Wang ◽  
...  
Keyword(s):  
Digital Simulation ◽  
Design Rule
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