Fault Tolerant Arithmetic Operations with Multiple Error Detection and Correction

2007 ◽  
Author(s):  
Mojtaba Valinataj ◽  
Saeed Safari
Keyword(s):  
Error Detection ◽  
Fault Tolerant ◽  
Arithmetic Operations ◽  
Error Detection And Correction ◽  
Multiple Error

scholarly journals Multiple Error Correction in Redundant Residue Number Systems: A Modified Modular Projection Method with Maximum Likelihood Decoding

2022 ◽  
Vol 12 (1) ◽  
pp. 463
Author(s):  
Mikhail Babenko ◽  
Anton Nazarov ◽  
Maxim Deryabin ◽  
Nikolay Kucherov ◽  
Andrei Tchernykh ◽  
...  
Keyword(s):  
Error Detection ◽  
Chinese Remainder Theorem ◽  
Number System ◽  
Maximum Likelihood Decoding ◽  
Number Systems ◽  
Residue Number Systems ◽  
Error Detection And Correction ◽  
Residue Number ◽  
Weighted Number ◽  
Multiple Error

Error detection and correction codes based on redundant residue number systems are powerful tools to control and correct arithmetic processing and data transmission errors. Decoding the magnitude and location of a multiple error is a complex computational problem: it requires verifying a huge number of different possible combinations of erroneous residual digit positions in the error localization stage. This paper proposes a modified correcting method based on calculating the approximate weighted characteristics of modular projections. The new procedure for correcting errors and restoring numbers in a weighted number system involves the Chinese Remainder Theorem with fractions. This approach calculates the rank of each modular projection efficiently. The ranks are used to calculate the Hamming distances. The new method speeds up the procedure for correcting multiple errors and restoring numbers in weighted form by an average of 18% compared to state-of-the-art analogs.

scholarly journals High-Performance and Energy-Efficient Fault Tolerance FPGA-to-FPGA Communication

2021 ◽  
Author(s):  
Naresh Kumar Reddy ◽  
Swamy Cherukuru ◽  
Veena Vani ◽  
Vishal Reddy
Keyword(s):  
Error Detection ◽  
High Speed ◽  
High Performance ◽  
Fault Tolerant ◽  
Key Factors ◽  
Error Detection And Correction ◽  
Performance Error ◽  
Increasing Demand ◽  
Accuracy Performance ◽  
Or Applications

Abstract These days, due to the increasing demand for high speed and parallel computation, several real world applications and systems include multiple FPGAs in them. Due to this, FPGAs often need to communicate among them. So, communication between the FPGAs is one of the key factors that determines the accuracy, performance and correctness of the entire multiple FPGAs systems or applications. This paper presents the design of an efficient multi-bit fault tolerant communication system for FPGA-to-FPGA communication. The proposed design is synthesized and also simulated through Vivado design suit 2018.3 and was communicated with two Kintex-7 FPGA boards. When compared with the existing FPGA-to-FPGA communication and inter FPGA communication designs, the proposed design have higher performance, error detection and correction capability.

scholarly journals Self Checking Design Technique for Numerical Computations

VLSI Design ◽  
1998 ◽  
Vol 5 (4) ◽  
pp. 385-392 ◽  
Author(s):  
F. S. Vainstein
Keyword(s):  
Error Detection ◽  
Substantial Reduction ◽  
Design Technique ◽  
Numerical Computations ◽  
Field Extensions ◽  
Class A ◽  
Error Detection And Correction ◽  
Algebraic Concepts ◽  
Class Of Functions ◽  
Multiple Error

The objective of this paper is to develop an efficient method for testing of numerical computations based on algebraic concepts such as transcendental degree of field extensions.A class of polynomially checkable functions is introduced, and for computation of the functions from this class a new method for error detection/error correction is proposed. This class of functions is shown to be large. The proposed method can also be extended to testing of computations of functions which are not polynomially checkable.The preliminary results show great potential of this approach. In particular the proposed approach will lead to substantial reduction in hardware overhead required for multiple error detection and correction, as compare to the check sum method and other existing techniques.

A GENERALIZED ABFT TECHNIQUE USING A FAULT TOLERANT NEURAL NETWORK

2007 ◽  
Vol 16 (03) ◽  
pp. 337-356 ◽  
Author(s):  
AMIR MOOSAVIE NIA ◽  
KARIM MOHAMMADI
Keyword(s):  
Neural Network ◽  
Error Detection ◽  
Fault Tolerant ◽  
Back Propagation ◽  
Back Propagation Algorithm ◽  
Output Error ◽  
Data Process ◽  
Error Detection And Correction ◽  
Gaussian Distribution Function ◽  
Sequence Simulation

In this paper, a measure of sensitivity is defined to evaluate fault tolerance of neural networks and we show that the sensitivity of a link is closely related to the amount of information passed through it. Based on this assumption, we prove that the distribution of output error caused by s-a-0 (stuck at 0) faults in an MLP network has a Gaussian distribution function. UDBP (Uniformly Distributed Back Propagation) algorithm is then introduced to minimize mean and variance of the output error. Then an MLP neural network trained with UDBP, contributes in an Algorithm-Based Fault Tolerant (ABFT) scheme to protect a nonlinear data process block. A systematic real convolution code guarantees that faults representing errors in the processed data will result in notable nonzero values in syndrome sequence. A majority logic decoder can now easily detect and correct single faults by observing the syndrome sequence. Simulation results demonstrating the error detection and correction behavior against random s-a-0 faults are presented too.

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