Test Generation for Single and Multiple Stuck-at Faults of a Combinational Circuit Designed by Covering Shared ROBDD with CLBs

2007 ◽  
Author(s):  
A. Matrosova ◽  
E. Loukovnikova ◽  
S. Ostanin ◽  
A. Zinchuck ◽  
E. Nikolaeva
Keyword(s):  
Test Generation ◽  
Combinational Circuit

Reduction of Combi-Fault Collapsing Using Maximum Fanout Branch Partitioning

2020 ◽  
Vol 17 (4) ◽  
pp. 1682-1687
Author(s):  
P. Pattunnarajam ◽  
Reeba Korah ◽  
Mariakalavathy
Keyword(s):  
Test Generation ◽  
Experimental Result ◽  
Combinational Circuit ◽  
Important Approach ◽  
Collapse Ratio

Combi-Fault collapsing is a very important approach to reduce linked stuck at faults and to cause effective faults in a combinational circuit. It can significantly moderate the problem of test generation and test work. In this paper, MAXFAN (Maximum Fanout Branch) partitioning is converted into gate level circuit with site of reconvergence into Fanout-Free Regions and implication of faulty values in the cone is passed over to identify checkpoint faults, equivalence and dominance faults. This method is to compute the tests for SSF (single stuck at faults) and consequently achieves low fault collapse ratio. Experimental result shows that max fanout partitioning reduces the number of checkpoints and also reduces the maximum number of faults with low collapse ratio.

Low Power and High Speed Sequential Circuits Test Architecture

2019 ◽  
Vol 12 ◽  
Author(s):  
Ahmed K. Jameil ◽  
Yasir Amer Abbas ◽  
Saad Al-Azawi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Test Generation ◽  
High Speed ◽  
Fir Filter ◽  
Sequential Circuits ◽  
Fir Filters ◽  
Design Verification ◽  
Sequential Circuit ◽  
Generation Algorithm

Background: The designed circuits are tested for faults detection in fabrication to determine which devices are defective. The design verification is performed to ensure that the circuit performs the required functions after manufacturing. Design verification is regarded as a test form in both sequential and combinational circuits. The analysis of sequential circuits test is more difficult than in the combinational circuit test. However, algorithms can be used to test any type of sequential circuit regardless of its composition. An important sequential circuit is the finite impulse response (FIR) filters that are widely used in digital signal processing applications. Objective: This paper presented a new design under test (DUT) algorithm for 4-and 8-tap FIR filters. Also, the FIR filter and the proposed DUT algorithm is implemented using field programmable gate arrays (FPGA). Method: The proposed test generation algorithm is implemented in VHDL using Xilinx ISE V14.5 design suite and verified by simulation. The test generation algorithm used FIR filtering redundant faults to obtain a set of target faults for DUT. The fault simulation is used in DUT to assess the benefit of test pattern in fault coverage. Results: The proposed technique provides average reductions of 20 % and 38.8 % in time delay with 57.39 % and 75 % reductions in power consumption and 28.89 % and 28.89 % slices reductions for 4- and 8-tap FIR filter, respectively compared to similar techniques. Conclusions: The results of implementation proved that a high speed and low power consumption design can be achieved. Further, the speed of the proposed architecture is faster than that of existing techniques.

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