Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) ◽

10.1109/dft.2007.12 ◽

2007 ◽

Cited By ~ 2

Author(s):

Rani S. Ghaida ◽

Payman Zarkesh-Ha

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