scholarly journals HEVC Based Multi-view Video Codec Using Frame Interleaving Technique

2016 ◽  
Author(s):  
Bruhanth Mallik ◽  
Akbar Sheikh Akbari
Keyword(s):  
Video Codec ◽  
Interleaving Technique

ОСОБЕННОСТИ АРХИТЕКТУРЫ И ОСНОВНЫЕ ХАРАКТЕРИСТИКИ АППАРАТНОГО ВИДЕОКОДЕКА СТАНДАРТА H.264 В СОСТАВЕ МИКРОСХЕМЫ 1892ВМ14Я

2020 ◽  
Vol 96 (3s) ◽  
pp. 89-96
Author(s):  
А.А. Беляев ◽  
Я.Я. Петричкович ◽  
Т.В. Солохина ◽  
И.А. Беляев
Keyword(s):  
Data Flow ◽  
System On Chip ◽  
Video Codec ◽  
Experimental Results ◽  
Video Sequences ◽  
Ip Core ◽  
Performance Measurements ◽  
Synchronization Mechanism ◽  
Architectural Features ◽  
On Chip

Рассмотрены особенности архитектуры и основные характеристики аппаратного видеокодека по стандарту H.264, входящего в состав микросхемы 1892ВМ14Я (MCom-02). Описан механизм синхронизации потоков данных на основе набора флагов событий. Приведены экспериментальные результаты измерения характеристик производительности разработанного видеокодека на реальных видеосюжетах при различных форматах передаваемого изображения. The paper considers main architectural features and characteristics of H.264 hardware video codec IP-core as a part of MCom- 02 system-on-chip (SoC). Bedides, it presents data flow synchronization mechanism based on event flags set, as well as experimental results of performance measurements for the designed video codec IP-core obtained for different video sequences and different image formats.

scholarly journals Decoder-driven mode decision in a block-based distributed video codec

2011 ◽  
Vol 58 (1) ◽  
pp. 239-266 ◽  
Author(s):  
Stefaan Mys ◽  
Jürgen Slowack ◽  
Jozef Škorupa ◽  
Nikos Deligiannis ◽  
Peter Lambert ◽  
...  
Keyword(s):  
Video Codec ◽  
Mode Decision ◽  
Block Based

CNN-Based Video Codec Classifier For Multimedia Forensics

2021 ◽  
Author(s):  
Rodrigo Pessoa ◽  
Anil Kokaram ◽  
Francois Pitie ◽  
Mark Sugrue
Keyword(s):  
Video Codec ◽  
Multimedia Forensics

A Novel HBE-MCM-Based Multiplier Architecture for 8-Point DCT Structure

2016 ◽  
Vol 26 (04) ◽  
pp. 1750054
Author(s):  
M. Kiruba ◽  
V. Sumathy
Keyword(s):  
Video Processing ◽  
Power Dissipation ◽  
Field Programmable Gate Array ◽  
Video Codec ◽  
Floating Point ◽  
Data Path ◽  
Image And Video Processing ◽  
Field Programmable ◽  
Minimum Number ◽  
Code Language

The Discrete Cosine Transform (DCT) structure plays a significant role in the signal processing applications such as image and video processing applications. In the traditional hardware design, the 8-point DCT architecture contains more number of logical slices in it. Also, it consists of number of multipliers to update the weight. This leads to huge area consumption and power dissipation in that architecture. To mitigate the conventional drawbacks, this paper presents a novel Hierarchical-based Expression (HBE)-Multiple Constant Multiplication (MCM)-based multiplier architecture design for the 8-point DCT structure used in the video CODEC applications. The proposed work involves modified data path architecture and Floating Point Processing Element (FPPE) architecture. Our proposed design of the multipliers and DCT architecture requires minimum number of components when compared to the traditional DCT method. The HBE-MCM-based multiplier architecture includes shifters and adders. The number of Flip-Flops (FFs) and Look Up Tables (LUTs) used in the proposed architecture is reduced. The power consumption is reduced due to the reduction in the size of the components. This design is synthesized in VERILOG code language and implemented in the Field Programmable Gate Array (FPGA). The performance of the proposed architecture is evaluated by comparing it with traditional DCT architecture in terms of the Number of FFs, Number of LUTs, area, power, delay and speed.

Sign in / Sign up

Export Citation Format

Share Document