scholarly journals Managing the Impact of On-chip Temperature on the Lifetime Reliability of Reliably Overclocked Systems

2009 ◽  
Author(s):  
Viswanathan Subramanian ◽  
Prem Kumar Ramesh ◽  
Arun K. Somani
Keyword(s):  
Chip Temperature ◽  
Lifetime Reliability ◽  
On Chip ◽  
The Impact

scholarly journals Thermographic Study of Chip Temperature in High-Speed Dry Milling Magnesium Alloys

2016 ◽  
Vol 7 (2) ◽  
pp. 86-92 ◽  
Author(s):  
Józef Kuczmaszewski ◽  
Ireneusz Zagórski ◽  
Piotr Zgórniak
Keyword(s):  
Temperature Measurement ◽  
Magnesium Alloys ◽  
High Speed ◽  
Machining Process ◽  
Dry Milling ◽  
Technological Parameters ◽  
Chip Temperature ◽  
Thermographic Study ◽  
On Chip ◽  
The Impact

Abstract This paper presents an overview of the state of knowledge on temperature measurement in the cutting area during magnesium alloy milling. Additionally, results of own research on chip temperature measurement during dry milling of magnesium alloys are included. Tested magnesium alloys are frequently used for manufacturing elements applied in the aerospace industry. The impact of technological parameters on the maximum chip temperature during milling is also analysed. This study is relevant due to the risk of chip ignition during the machining process.

scholarly journals Design of a Real-Time Breakdown Voltage and On-Chip Temperature Monitoring System for Single Photon Avalanche Diodes

Electronics ◽  
2020 ◽  
Vol 10 (1) ◽  
pp. 25
Author(s):  
Shijie Deng ◽  
Alan P. Morrison ◽  
Yong Guo ◽  
Chuanxin Teng ◽  
Ming Chen ◽  
...  
Keyword(s):  
Real Time ◽  
Breakdown Voltage ◽  
Count Rate ◽  
Single Photon ◽  
Photon Counting ◽  
Temperature Monitoring ◽  
Dark Count ◽  
Chip Temperature ◽  
Avalanche Diodes ◽  
On Chip

The design and implementation of a real-time breakdown voltage and on-chip temperature monitoring system for single photon avalanche diodes (SPADs) is described in this work. In the system, an on-chip shaded (active area of the detector covered by a metal layer) SPAD is used to provide a dark count rate for the breakdown voltage and temperature calculation. A bias circuit was designed to provide a bias voltage scanning for the shaded SPAD. A microcontroller records the pulses from the anode of the shaded SPAD and calculates its real-time dark count rate. An algorithm was developed for the microcontroller to calculate the SPAD’s breakdown voltage and the on-chip temperature in real time. Experimental results show that the system is capable of measuring the SPAD’s breakdown voltage with a mismatch of less than 1.2%. Results also show that the system can provide real-time on-chip temperature monitoring for the range of −10 to 50 °C with errors of less than 1.7 °C. The system proposed can be used for the real-time SPAD’s breakdown voltage and temperature estimation for dual-SPADs or SPAD arrays chip where identical detectors are fabricated on the same chip and one or more dummy SPADs are shaded. With the breakdown voltage and the on-chip temperature monitoring, intelligent control logic can be developed to optimize the performance of the SPAD-based photon counting system by adjusting the parameters such as excess bias voltage and dead-time. This is particularly useful for SPAD photon counting systems used in complex working environments such as the applications in 3D LIDAR imaging for geodesy, geology, geomorphology, forestry, atmospheric physics and autonomous vehicles.

Analysis of Thermal Properties of Power Multifinger HEMT Devices

2018 ◽  
Author(s):  
Aleš Chvála ◽  
Robert Szobolovszký ◽  
Jaroslav Kováč ◽  
Martin Florovič ◽  
Juraj Marek ◽  
...  
Keyword(s):  
Temperature Distribution ◽  
Thermal Management ◽  
High Electron Mobility Transistor ◽  
Structure Design ◽  
High Electron ◽  
Design And Optimization ◽  
Chip Temperature ◽  
Materials Used ◽  
On Chip ◽  
Measurement Approach

In this paper, several methods suitable for real time on-chip temperature measurements of power AlGaN/GaN based high-electron mobility transistor (HEMT) grown on SiC substrate are presented. The measurement of temperature distribution on HEMT surface using Raman spectroscopy is presented. We have deployed a temperature measurement approach utilizing electrical I-V characteristics of the neighboring Schottky diode under different dissipated power of the transistor heat source. These methods are verified by measurements with micro thermistors. The results show that these methods have a potential for HEMT analysis in thermal management. The features and limitations of the proposed methods are discussed. The thermal parameters of materials used in the device are extracted from temperature distribution in the structure with the support of 3-D device thermal simulation. The thermal analysis of the multifinger power HEMT is performed. The effects of the structure design and fabrication processes from semiconductor layers, metallization, and packaging up to cooling solutions are investigated. The analysis of thermal behavior can help during design and optimization of power HEMT.

Study of the Impact of Protective Process Agents with Carbon Nanopowder Additives on Chip Forming Processes

2021 ◽  
Vol 887 ◽  
pp. 319-324
Author(s):  
E.A. Petrovsky ◽  
K.A. Bashmur ◽  
Vadim S. Tynchenko
Keyword(s):  
Experimental Studies ◽  
Cutting Speed ◽  
Optimal Composition ◽  
Cooling Process ◽  
Shrinkage Ratio ◽  
Nickel Chromium ◽  
Chromium Alloys ◽  
On Chip ◽  
The Impact ◽  
Positive Effect

The present study describes the impact of various protective process agents on chip forming processes. The research was conducted on NiCr20TiAl and 34NiCrMoV14-5 nickel-chromium alloys. New lubricant-cooling process agents with carbon nanopowder additives are studied. The optimal composition of the nanopowder additive and its effect during alloy cutting is examined. Experiments reveal the dependence of shrinkage ratio on cutting speed and various protective process agents. The values of H50 microhardness are also defined when cutting these alloys using protective process agents. Experimental studies found the positive effect of developed agents with nanopowder additives on the processes of NiCr20TiAl and 34NiCrMoV14-5 alloys chip formation.

Efficiency Analysis of Approaches for Temperature Management and Task Mapping in Networks-on-Chip

2014 ◽  
pp. 368-398
Author(s):  
Tim Wegner ◽  
Martin Gag ◽  
Dirk Timmermann
Keyword(s):  
Thermal Management ◽  
System Performance ◽  
Task Mapping ◽  
Systematic Analysis ◽  
Networks On Chip ◽  
Chip Temperature ◽  
Management Measures ◽  
Mapping Process ◽  
On Chip ◽  
And Task

With the progress of deep submicron technology, power consumption and temperature-related issues have become dominant factors for chip design. Therefore, very large-scale integrated systems like Systems-on-Chip (SoCs) are exposed to an increasing thermal stress. On the one hand, this necessitates effective mechanisms for thermal management and task mapping. On the other hand, application of according thermal-aware approaches is accompanied by disturbance of system integrity and degradation of system performance. In this chapter, a method to predict and proactively manage the on-chip temperature distribution of systems based on Networks-on-Chip (NoCs) is proposed. Thereby, traditional reactive approaches for thermal management and task mapping can be replaced. This results in shorter response times for the application of management measures and therefore in a reduction of temperature and thermal imbalances and causes less impairment of system performance. The systematic analysis of simulations conducted for NoC sizes up to 4x4 proves that under certain conditions the proactive approach is able to mitigate the negative impact of thermal management on system performance while still improving the on-chip temperature profile. Similar effects can be observed for proactive thermal-aware task mapping at system runtime allowing for the consideration of prospective thermal conditions during the mapping process.

Designing of High Performance Multicore Processor with Improved Cache Configuration and Interconnect

2016 ◽  
pp. 204-219
Author(s):  
Ram Prasad Mohanty ◽  
Ashok Kumar Turuk ◽  
Bibhudatta Sahoo
Keyword(s):  
High Performance ◽  
Multicore Processors ◽  
Multicore Processor ◽  
Cache Size ◽  
L2 Cache ◽  
Internal Network ◽  
On Chip ◽  
L1 And L2 ◽  
The Impact ◽  
Cache Configuration

The growing number of cores increases the demand for a powerful memory subsystem which leads to enhancement in the size of caches in multicore processors. Caches are responsible for giving processing elements a faster, higher bandwidth local memory to work with. In this chapter, an attempt has been made to analyze the impact of cache size on performance of Multi-core processors by varying L1 and L2 cache size on the multicore processor with internal network (MPIN) referenced from NIAGRA architecture. As the number of core's increases, traditional on-chip interconnects like bus and crossbar proves to be low in efficiency as well as suffer from poor scalability. In order to overcome the scalability and efficiency issues in these conventional interconnect, ring based design has been proposed. The effect of interconnect on the performance of multicore processors has been analyzed and a novel scalable on-chip interconnection mechanism (INOC) for multicore processors has been proposed. The benchmark results are presented by using a full system simulator. Results show that, using the proposed INoC, compared with the MPIN; the execution time are significantly reduced.

Performance Analysis of On-Chip Communication Structures under Device Variability

2010 ◽  
Vol 1 (4) ◽  
pp. 40-62
Author(s):  
Faiz-ul Hassan ◽  
Wim Vanderbauwhede ◽  
Fernando Rodríguez-Salazar
Keyword(s):  
Communication Networks ◽  
Data Storage ◽  
Failure Probability ◽  
Analytical Models ◽  
High Yield ◽  
Communication Link ◽  
Link Failure ◽  
Communication Structures ◽  
On Chip ◽  
The Impact

On-chip communication is becoming an important bottleneck in the design and operation of high performance systems where it has to face additional challenges due to device variability. Communication structures such as tapered buffer drivers, interconnects, repeaters, and data storage elements are vulnerable to variability, which can limit the performance of the on-chip communication networks. In this regard, it becomes important to have a complete understanding of the impact that variability will have on the performance of these circuit elements in order to design high yield and reliable systems. In this paper, the authors have characterized the performance of the communication structures under the impact of random dopant fluctuation (RDF) for the future technology generations of 25, 18, and 13 nm. For accurate characterization of their performance, a Monte Carlo simulation method has been used along with predictive device models for the given technologies. Analytical models have been developed for the link failure probability of a repeater inserted interconnect which uses characterization data of all communication structures to give an accurate prediction of the link failure probability. The model has also been extended to calculate the link failure probability of a wider communication link.

A ±0.15% RH Inaccuracy Humidity Sensing System With ±0.44 °C (3σ) Inaccuracy On-Chip Temperature Sensor

2021 ◽  
Vol 21 (2) ◽  
pp. 2115-2123
Author(s):  
Jaehoon Jun ◽  
Sangmin Shin ◽  
Minsung Kim ◽  
Yongjoon Ahn ◽  
Suhwan Kim
Keyword(s):  
Temperature Sensor ◽  
Humidity Sensing ◽  
Chip Temperature ◽  
Sensing System ◽  
On Chip
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