scholarly journals Design and Implementation of a High-Performance Microprocessor Cache Compression Algorithm

2008 ◽  
Author(s):  
Xi Chen ◽  
Lei Yang ◽  
Haris Lekatsas ◽  
Robert P. Dick ◽  
Li Shang
Keyword(s):  
High Performance ◽  
Compression Algorithm ◽  
Design And Implementation ◽  
Cache Compression

C-Pack: A High-Performance Microprocessor Cache Compression Algorithm

2010 ◽  
Vol 18 (8) ◽  
pp. 1196-1208 ◽  
Author(s):  
Xi Chen ◽  
Lei Yang ◽  
Robert P Dick ◽  
Li Shang ◽  
Haris Lekatsas
Keyword(s):  
High Performance ◽  
Compression Algorithm ◽  
Cache Compression

scholarly journals Design and implementation of CNTFET based ternary 1x1 memories

2019 ◽  
Vol 8 (3) ◽  
pp. 175 ◽  
Author(s):  
S.Tamil Selvan ◽  
M. Sundararajan
Keyword(s):  
High Performance ◽  
Data Access ◽  
Cmos Technology ◽  
Access Time ◽  
The Novel ◽  
Design And Implementation ◽  
Technology Process ◽  
Sram Cell ◽  
And Performance ◽  
Power Application

In this paper presented Design and implementation of CNTFET based Ternary 1x1 RAM memories high-performance digital circuits. CNTFET Ternary 1x1 SRAM memories is implement using 32nm technology process. The CNTFET decresase the diameter and performance matrics like delay,power and power delay, The CNTFET Ternary 6T SRAM cell consists of two cross coupled Ternary inverters one is READ and another WRITE operations of the Ternary 6T SRAM cell are performed with the Tritline using HSPICE and Tanner tools in this tool is performed high accuracy. The novel based work can be used for Low Power Application and Access time is less of compared to the conventional CMOS Technology. The CNTFET Ternary 6T SRAM array module (1X1) in 32nm technology consumes only 0.412mW power and data access time is about 5.23ns.

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