Traffic-aware power-gating scheme for Network-on-Chip routers

2016 ◽  
Author(s):  
Nasim Nasirian ◽  
Reza Soosahabi ◽  
Magdy Bayoumi
Keyword(s):  
Network On Chip ◽  
Power Gating ◽  
On Chip ◽  
Gating Scheme

Probabilistic Analysis of Power-Gating in Network-on-Chip Routers

2019 ◽  
Vol 66 (2) ◽  
pp. 242-246 ◽  
Author(s):  
Nasim Nasirian ◽  
Reza Soosahabi ◽  
Magdy A. Bayoumi
Keyword(s):  
Probabilistic Analysis ◽  
Network On Chip ◽  
Power Gating ◽  
On Chip

scholarly journals Power‐gating technique for network‐on‐chip buffers

2013 ◽  
Vol 49 (23) ◽  
pp. 1438-1440 ◽  
Author(s):  
M.R. Casu ◽  
M.K. Yadav ◽  
M. Zamboni
Keyword(s):  
Network On Chip ◽  
Power Gating ◽  
On Chip

scholarly journals Applying Partial Power-Gating to Direction-Sliced Network-on-Chip

2015 ◽  
Vol 2015 ◽  
pp. 1-16 ◽  
Author(s):  
Feng Wang ◽  
Xiantuo Tang ◽  
Zuocheng Xing
Keyword(s):  
Power Efficiency ◽  
Network Performance ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Leakage Power ◽  
Power Gating ◽  
Load Range ◽  
Communication Architectures ◽  
On Chip ◽  
Many Core

Network-on-Chip (NoC) is one of critical communication architectures for future many-core systems. As technology is continually scaling down, on-chip network meets the increasing leakage power crisis. As a leakage power mitigation technique, power-gating can be utilized in on-chip network to solve the crisis. However, the network performance is severely affected by the disconnection in the conventional power-gated NoC. In this paper, we propose a novel partial power-gating approach to improve the performance in the power-gated NoC. The approach mainly involves a direction-slicing scheme, an improved routing algorithm, and a deadlock recovery mechanism. In the synthetic traffic simulation, the proposed design shows favorable power-efficiency at low-load range and achieves better performance than the conventional power-gated one. For the application trace simulation, the design in the mesh/torus network consumes 15.2%/18.9% more power on average, whereas it can averagely obtain 45.0%/28.7% performance improvement compared with the conventional power-gated design. On balance, the proposed design with partial power-gating has a better tradeoff between performance and power-efficiency.

A Voting Approach for Adaptive Network-on-Chip Power-Gating

2020 ◽  
pp. 1-1
Author(s):  
Jiayi Huang ◽  
Shilpa Bhosekar ◽  
Rahul Boyapati ◽  
Ningyuan Wang ◽  
Byul Hur ◽  
...  
Keyword(s):  
Network On Chip ◽  
Power Gating ◽  
Adaptive Network ◽  
On Chip

Applying partial power-gating to bit-sliced network-on-chip

2015 ◽  
Vol 46 (11) ◽  
pp. 1002-1011
Author(s):  
Feng Wang ◽  
Xiantuo Tang ◽  
Zuocheng Xing
Keyword(s):  
Network On Chip ◽  
Power Gating ◽  
On Chip

BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers

2017 ◽  
Vol 104 ◽  
pp. 130-145 ◽  
Author(s):  
Davide Zoni ◽  
Andrea Canidio ◽  
William Fornaciari ◽  
Panayiotis Englezakis ◽  
Chrysostomos Nicopoulos ◽  
...  
Keyword(s):  
Network On Chip ◽  
Power Gating ◽  
Fine Grained ◽  
On Chip
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