Towards energy efficient hybrid on-chip Scratch Pad Memory with non-volatile memory

Author(s):  
Jingtong Hu ◽  
C J Xue ◽  
Qingfeng Zhuge ◽  
Wei-Che Tseng ◽  
E H.-M Sha
AIP Advances ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 025111 ◽  
Author(s):  
Divya Kaushik ◽  
Utkarsh Singh ◽  
Upasana Sahu ◽  
Indu Sreedevi ◽  
Debanjan Bhowmik

2008 ◽  
Vol 60 (2) ◽  
pp. 149-168 ◽  
Author(s):  
Mohammed G. Khatib ◽  
Pieter H. Hartel ◽  
Hylke W. van Dijk

Author(s):  
Shota Matsuno ◽  
Masashi Tawada ◽  
Masao Yanagisawa ◽  
Shinji Kimura ◽  
Nozomu Togawa ◽  
...  

2014 ◽  
Vol 644-650 ◽  
pp. 3421-3425
Author(s):  
Ming Qian Wang ◽  
Jie Tao Diao ◽  
Nan Li ◽  
Xi Wang ◽  
Kai Bu

NVM has become a promising technology to partly replace SRAM as on-chip cache and reduce the gap between the core and cache. To take all advantages of NVM and SRAM, we propose a Hybrid Cache, constructing on-chip cache hierarchies with different technologies. As shown in article, hybrid cache performance and power consumption of Hybrid Cache have a large advantage over caches base on single technologies. In addition, we have shown some other methods that can optimize the performance of hybrid cache.


2014 ◽  
Vol 104 (23) ◽  
pp. 232403 ◽  
Author(s):  
Ayan K. Biswas ◽  
Supriyo Bandyopadhyay ◽  
Jayasimha Atulasimha

Sign in / Sign up

Export Citation Format

Share Document