A link arbitration scheme for quality of service in a latency-optimized network-on-chip

2009 ◽  
Author(s):  
Jonas Diemer ◽  
Rolf Ernst
Keyword(s):  
Quality Of Service ◽  
Network On Chip ◽  
On Chip

Quality-of-service and error control techniques for mesh-based network-on-chip architectures

Integration ◽  
2005 ◽  
Vol 38 (3) ◽  
pp. 353-382 ◽  
Author(s):  
Praveen Vellanki ◽  
Nilanjan Banerjee ◽  
Karam S. Chatha
Keyword(s):  
Quality Of Service ◽  
Error Control ◽  
Network On Chip ◽  
Control Techniques ◽  
On Chip

New design of Network on Chip Based on Virtual Routers

2016 ◽  
Vol 2 (1) ◽  
pp. 115 ◽  
Author(s):  
Mohamed Fehmi Chatmen ◽  
Adel Baganne ◽  
Rached Tourki
Keyword(s):  
Quality Of Service ◽  
Integrated Circuits ◽  
Network On Chip ◽  
Dimensional Network ◽  
3D Integrated Circuits ◽  
Average Latency ◽  
Improved Performance ◽  
Virtual Routers ◽  
On Chip

<p>Network is considered the most convenient way to communicate between different IP integrated into the same chip. Studies have been developed to propose networks with improved performance in terms of latency, power consumption, throughput and quality of service. Most of these networks have been designed based on the 2-dimensional network structure. Recently, with the introduction of the new structure of 3D integrated circuits (3D IC), new works have used this type of circuit to design 3 dimensions on-chip networks. The advantage brought by this new structure is to reduce the average number of hops crossed from the source to the destination, which improves the throughput and the average latency of the network.</p>

scholarly journals Design and Implementation of a Efficient Router using X Y Algorithm

2021 ◽  
pp. 5-9
Author(s):  
Geethanjali N ◽  
◽  
Dr. Rekha K.R ◽  
Keyword(s):  
Quality Of Service ◽  
Dynamic Reconfiguration ◽  
Network On Chip ◽  
Packet Size ◽  
Network Configuration ◽  
Design And Implementation ◽  
Transport Plan ◽  
On Chip ◽  
High Information

The engineering for on chip network configuration utilizing dynamic reconfiguration is an answer for Communication Interfaces, Chip cost, Quality of Service, ensure adaptability of the organization. The proposed engineering powerfully arrange itself concerning Hardware Modules like switches, Switch based packet , information to a packet size with changing the correspondence situation and its prerequisites on run time. The NOC Architecture assumes urgent part while planning correspondence frameworks intended for SOC. The NOC engineering be better over traditional transport, mutual transport plan , cross bar interconnection design intended for on chip organizations. In a greater part of the NO C engineering contains lattice, torus or different geographies to plan solid switch. In any case, the greater part of the plans are neglects to advance a Quality of Service, blocking issues, cost, Chip as well as mostly plan throughput, region transparency with inactivity. Proposed plan we are planning a reconfigurable switch for network on chip plan that improve the correspondence performance. The proposed configuration dodges the restrictions of transport based interconnection plans which are frequently applied in part progressively reconfigurable FPGA plans. . With the assistance of this switch plan we can accomplish low inactivity and high information throughput.

A Quality of Service Network on Chip based on a new priority arbitration mechanism

2011 ◽  
Author(s):  
Chouchene Wissem ◽  
Brahim Attia ◽  
Abid Noureddine ◽  
Abdelkrim Zitouni ◽  
Rached Tourki
Keyword(s):  
Quality Of Service ◽  
Network On Chip ◽  
Service Network ◽  
On Chip

scholarly journals Design and Implementation of a Efficient Router using X Y Algorithm

2021 ◽  
Vol 1 (3) ◽  
pp. 5-9
Author(s):  
Geethanjali .N ◽  
Rekha K.R.
Keyword(s):  
Quality Of Service ◽  
Dynamic Reconfiguration ◽  
Network On Chip ◽  
Packet Size ◽  
Network Configuration ◽  
Design And Implementation ◽  
Transport Plan ◽  
On Chip ◽  
High Information

The engineering for on chip network configuration utilizing dynamic reconfiguration is an answer for Communication Interfaces, Chip cost ,Quality of Service, ensure adaptability of the organization. The proposed engineering powerfully arrange itself concerning Hardware Modules like switches, Switch based packet , information to a packet size with changing the correspondence situation and its prerequisites on run time. The NOC Architecture assumes urgent part while planning correspondence frameworks intended for SOC. The NOC engineering be better over traditional transport, mutual transport plan , cross bar interconnection design intended for on chip organizations. In a greater part of the NO C engineering contains lattice, torus or different geographies to plan solid switch. In any case, the greater part of the plans are neglects to advance a Quality of Service, blocking issues, cost, Chip as well as mostly plan throughput, region transparency with inactivity. Proposed plan we are planning a reconfigurable switch for network on chip plan that improve the correspondence performance. The proposed configuration dodges the restrictions of transport based interconnection plans which are frequently applied in part progressively reconfigurable FPGA plans. . With the assistance of this switch plan we can accomplish low inactivity and high information throughput.

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