Hardware Scheduling Support in SMP Architectures

2007 ◽  
Author(s):  
Andre C. Nacul ◽  
Francesco Regazzoni ◽  
Marcello Lajolo
Keyword(s):  
Hardware Scheduling

ON THE CORRECTNESS OF HARDWARE SCHEDULING MECHANISMS FOR OUT-OF-ORDER EXECUTION

1998 ◽  
Vol 08 (02) ◽  
pp. 301-314
Author(s):  
SILVIA M. MUELLER ◽  
WOLFGANG J. PAUL
Keyword(s):  
Sufficient Conditions ◽  
Instruction Level Parallelism ◽  
Scheduling Mechanisms ◽  
Level Parallelism ◽  
Order Execution ◽  
Hardware Scheduling

Hardware scheduling mechanisms are commonly used in current processors in order to make better use of instruction level parallelism. So far, such a mechanism is considered to be correct, if it avoids the standard structural and data hazards. However, based on two classical scheduling mechanisms, it will be shown that this condition is neither sufficient nor necessary for the correctness of such a mechanism, and that deadlocks are a serious matter in out-of-order execution as well. In addition, the paper provides sufficient conditions for the correctness of scheduling mechanisms.

Kernel-to-User-Mode Transition-Aware Hardware Scheduling

IEEE Micro ◽  
2015 ◽  
Vol 35 (4) ◽  
pp. 37-47
Author(s):  
Nikola Markovic ◽  
Daniel Nemirovsky ◽  
Osman Unsal ◽  
Mateo Valero ◽  
Adrian Cristal
Keyword(s):  
Mode Transition ◽  
Hardware Scheduling

Architectural support for task scheduling: hardware scheduling for dataflow on NUMA systems

2015 ◽  
Vol 71 (6) ◽  
pp. 2309-2338 ◽  
Author(s):  
Behram Khan ◽  
Daniel Goodman ◽  
Salman Khan ◽  
Will Toms ◽  
Paolo Faraboschi ◽  
...  
Keyword(s):  
Task Scheduling ◽  
Architectural Support ◽  
Hardware Scheduling
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