Instruction Trace Compression for Rapid Instruction Cache Simulation

2007 Design, Automation & Test in Europe Conference & Exhibition ◽

10.1109/date.2007.364389 ◽

2007 ◽

Cited By ~ 3

Author(s):

Andhi Janapsatya ◽

Aleksandar Ignjatovic ◽

Sri Parameswaran ◽

Joerg Henkel

Keyword(s):

Instruction Cache ◽

Cache Simulation ◽

Trace Compression

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Fast instruction cache analysis via static cache simulation

Proceedings of Simulation Symposium ◽

10.1109/simsym.1995.393589 ◽

2002 ◽

Cited By ~ 11

Author(s):

F. Mueller ◽

D.B. Whalley

Keyword(s):

Instruction Cache ◽

Cache Simulation ◽

Cache Analysis

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Fast instruction cache simulation strategies in a hardware/software co-design environment

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) ◽

10.1109/aspdac.1999.760030 ◽

1999 ◽

Cited By ~ 5

Author(s):

M. Lajolo ◽

L. Lavagno ◽

A. Sangiovanni-Vincentelli

Keyword(s):

Design Environment ◽

Instruction Cache ◽

Cache Simulation

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Compositional static instruction cache simulation

Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools - LCTES '04 ◽

10.1145/997163.997183 ◽

2004 ◽

Cited By ~ 3

Author(s):

Kaustubh Patil ◽

Kiran Seth ◽

Frank Mueller

Keyword(s):

Instruction Cache ◽

Cache Simulation

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Compositional static instruction cache simulation

ACM SIGPLAN Notices ◽

10.1145/998300.997183 ◽

2004 ◽

Vol 39 (7) ◽

pp. 136-145

Author(s):

Kaustubh Patil ◽

Kiran Seth ◽

Frank Mueller

Keyword(s):

Instruction Cache ◽

Cache Simulation

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A trace-capable instruction cache for cost efficient real-time program trace compression in SoC

Proceedings of the 46th Annual Design Automation Conference on ZZZ - DAC '09 ◽

10.1145/1629911.1629952 ◽

2009 ◽

Cited By ~ 4

Author(s):

Chun-Hung Lai ◽

Fu-Ching Yang ◽

Chung-Fu Kao ◽

Ing-Jer Huang

Keyword(s):

Real Time ◽

Instruction Cache ◽

Trace Compression ◽

Cost Efficient

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Efficient instruction cache simulation and execution profiling with a threaded-code interpreter

Proceedings of the 29th conference on Winter simulation - WSC '97 ◽

10.1145/268437.268745 ◽

1997 ◽

Cited By ~ 1

Author(s):

Peter S. Magnusson

Keyword(s):

Instruction Cache ◽

Cache Simulation

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A Trace-Capable Instruction Cache for Cost-Efficient Real-Time Program Trace Compression in SoC

IEEE Transactions on Computers ◽

10.1109/tc.2010.194 ◽

2011 ◽

Vol 60 (12) ◽

pp. 1665-1677 ◽

Cited By ~ 4

Author(s):

Chun-Hung Lai ◽

Fu-Ching Yang ◽

Ing-Jer Huang

Keyword(s):

Real Time ◽

Instruction Cache ◽

Trace Compression ◽

Cost Efficient

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Filtering drowsy instruction cache to achieve better efficiency

Proceedings of the 2008 ACM symposium on Applied computing - SAC '08 ◽

10.1145/1363686.1364050 ◽

2008 ◽

Author(s):

Roberto Giorgi ◽

Paolo Bennati

Keyword(s):

Instruction Cache

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Evaluating instruction cache vulnerability to transient errors

Proceedings of the 2005 workshop on MEmory performance DEaling with Applications, systems and architectures - MEDEA '06 ◽

10.1145/1166133.1166136 ◽

2006 ◽

Cited By ~ 6

Author(s):

Jun Yan ◽

Wei Zhang

Keyword(s):

Instruction Cache ◽

Transient Errors

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A case for shared instruction cache on chip multiprocessors running OLTP

ACM SIGARCH Computer Architecture News ◽

10.1145/1024295.1024297 ◽

2004 ◽

Vol 32 (3) ◽

pp. 11-18 ◽

Cited By ~ 3

Author(s):

Partha Kundu ◽

Murali Annavaram ◽

Trung Diep ◽

John Shen

Keyword(s):

Chip Multiprocessors ◽

Instruction Cache ◽

On Chip

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