Architecture-level performance estimation for IP-based embedded systems

Performance estimation for embedded systems with data and control dependencies

Proceedings of the Eighth International Workshop on Hardware/Software Codesign. CODES 2000 (IEEE Cat. No.00TH8518) ◽

10.1109/hsc.2000.843708 ◽

2002 ◽

Author(s):

P. Pop ◽

P. Eles ◽

Zebo Peng

Keyword(s):

Embedded Systems ◽

Performance Estimation ◽

And Control

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Performance Analysis of Dual Vt Domino Circuits with P-V-T Variations

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.88-89.326 ◽

2011 ◽

Vol 88-89 ◽

pp. 326-330 ◽

Cited By ~ 1

Author(s):

Jin Hui Wang ◽

Na Gong ◽

Gang Liu ◽

Shu Qin Geng ◽

Wu Chen Wu

Keyword(s):

Monte Carlo ◽

Monte Carlo Method ◽

Performance Analysis ◽

Leakage Current ◽

Active Power ◽

Performance Estimation ◽

Temperature Variations ◽

Multiple Parameter ◽

Domino Circuits ◽

Level Performance

The leakage current, active power and delay characterizations of the domino circuits in the presence of P-V-T (Process, Voltage, and Temperature) variations are analyzed based on multiple-parameter Monte Carlo method. It is demonstrated that failing to account for P-V-T variations and process-electro-thermal couplings can result in significant inaccuracy in transistor-level performance estimation. It also indicates that under significant P-V-T variations, DTV (Dual VtTechnology) is still highly effective to reduce the leakage current and active power for domino circuits, but induces speed penalty. At last, the robustness of different domino circuits with DTV against the P-V-T variations is discussed.

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High level performance estimation for a primitive operator filter FPGA

ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187) ◽

10.1109/iscas.1998.694453 ◽

2002 ◽

Cited By ~ 1

Author(s):

T. Arslan ◽

H.I. Eskikurt ◽

D.H. Horrocks

Keyword(s):

Performance Estimation ◽

High Level ◽

Level Performance

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Rapid, High-Level Performance Estimation for DSE Using Calibrated Weight Tables

System Level Design from HW/SW to Memory for Embedded Systems - IFIP Advances in Information and Communication Technology ◽

10.1007/978-3-319-90023-0_16 ◽

2017 ◽

pp. 197-209

Author(s):

Kasra Moazzemi ◽

Smit Patel ◽

Shen Feng ◽

Gunar Schirner

Keyword(s):

Performance Estimation ◽

High Level ◽

Level Performance

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SystemC Platform Modeling for Behavioral Simulation and Performance Estimation of Embedded Systems

Behavioral Modeling for Embedded Systems and Technologies ◽

10.4018/978-1-60566-750-8.ch009 ◽

2010 ◽

pp. 219-243 ◽

Cited By ~ 5

Author(s):

Hector Posadas ◽

Juan Castillo ◽

David Quijano ◽

Victor Fernandez ◽

Eugenio Villar ◽

...

Keyword(s):

Embedded Systems ◽

Design Space Exploration ◽

Performance Metrics ◽

System Modeling ◽

Performance Estimation ◽

Behavioral Simulation ◽

Close Interaction ◽

Accurate Performance ◽

And Performance ◽

On Chip

Currently, embedded systems make use of large, multiprocessing systems on chip integrating complex application software running on the different processors in close interaction with the application-specific hardware. These systems demand new modeling, simulation, and performance estimation tools and methodologies for system architecture evaluation and design exploration. Recently approved as IEEE 1666 standard, SystemC has proven to be a powerful language for system modeling and simulation. In this chapter, SCoPE, a SystemC framework for platform modeling, SW source-code behavioral simulation and performance estimation of embedded systems is presented. Using SCoPE, the application SW running on the different processors of the platform can be simulated efficiently in close interaction with the rest of the platform components. In this way, fast and sufficiently accurate performance metrics are obtained for design-space exploration.

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