Cost-performance trade-offs in networks on chip: a simulation-based approach

2004 ◽  
Author(s):  
S.G. Pestana ◽  
E. Rijpkema ◽  
A. Radulescu ◽  
K. Goossens ◽  
O.P. Gangwal
Keyword(s):  
Cost Performance ◽  
Networks On Chip ◽  
Trade Offs ◽  
Simulation Based ◽  
On Chip

Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip

2003 ◽  
Vol 150 (5) ◽  
pp. 294 ◽  
Author(s):  
E. Rijpkema ◽  
K. Goossens ◽  
A. Rdulescu ◽  
J. Dielissen ◽  
J. van Meerbergen ◽  
...  
Keyword(s):  
Best Effort ◽  
Networks On Chip ◽  
Trade Offs ◽  
On Chip

FXY: A HIERARCHICAL ROUTING ALGORITHM TO BALANCE PERFORMANCE AND FAULT TOLERANCE IN NETWORKS-ON-CHIP

2014 ◽  
Vol 23 (10) ◽  
pp. 1450146 ◽  
Author(s):  
SALEH FAKHRALI ◽  
HAMID R. ZARANDI
Keyword(s):  
Fault Tolerance ◽  
Fault Tolerant ◽  
Routing Algorithm ◽  
Experimental Results ◽  
Balance Performance ◽  
Networks On Chip ◽  
Large Size ◽  
Trade Offs ◽  
And Performance ◽  
On Chip

This paper presents a hierarchical fault-tolerant routing algorithm called FXY, which is a hybrid method based on flooding and XY, and can balance performance and fault tolerance based on a predefined parameter m. First, FXY partitions the whole network into different equal size square submeshes with the size of m × m. At the first level of the hierarchy, packet routing within these submeshes is performed based on flooding routing algorithm. When the packets are received at effective boundary of each submesh, XY routing is performed to route the packet inter submeshes i.e., from one submesh to the neighbor submesh which is certainly one of its neighbor nodes. Here, the size of the submesh is defined as fault-tolerant granularity. As fault-tolerant granularity is increased, the size of the submeshes will be increased, therefore the method mainly floods packets in large-size submeshes and finally packets are received at their destinations correctly. On the other hand, when fault-tolerant granularity is decreased, the method mainly routes packets as XY method, which is not fault-tolerant, but has the best performance. The method is evaluated for various packet injection rates and fault rates. The experimental results reveal that the method presents a fault-tolerant routing algorithm, and can be adjusted so that it shows better fault-tolerance and performance trade-offs compared to XY and flooding which are two end-to-end cases of having the best performance and no fault-tolerance, having the least performance and the best fault tolerance, respectively. The experimental results for an 8 × 8 NoC size, have shown that 2-FXY, which is the proposed method with fault-tolerant granularity of two, offers the best trade-off between performance and fault tolerance compared to other methods, XY, flooding and probabilistic flooding.

Trade-offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip

2008 ◽  
pp. 125-139 ◽  
Author(s):  
E. Rijpkema ◽  
K. G. W. Goossens ◽  
A. Rădulescu ◽  
J. Dielissen ◽  
J. van Meerbergen ◽  
...  
Keyword(s):  
Best Effort ◽  
Networks On Chip ◽  
Trade Offs ◽  
On Chip

Energy-Performance Analysis and Optimization for Networks-on-Chip

2014 ◽  
Vol 36 (5) ◽  
pp. 988-1003 ◽  
Author(s):  
Shuai ZHANG ◽  
Feng-Long SONG ◽  
Dong WANG ◽  
Zhi-Yong LIU ◽  
Dong-Rui FAN
Keyword(s):  
Performance Analysis ◽  
Energy Performance ◽  
Networks On Chip ◽  
On Chip

scholarly journals Ray Tracing Modeling of Electromagnetic Propagation for On-Chip Wireless Optical Communications

2018 ◽  
Vol 8 (4) ◽  
pp. 39 ◽  
Author(s):  
Franco Fuschini ◽  
Marina Barbiroli ◽  
Marco Zoli ◽  
Gaetano Bellanca ◽  
Giovanna Calò ◽  
...  
Keyword(s):  
Ray Tracing ◽  
Path Loss ◽  
Wireless Channel ◽  
Electromagnetic Propagation ◽  
Networks On Chip ◽  
Spatial Properties ◽  
Radiation Properties ◽  
Wireless Optical Communications ◽  
On Chip ◽  
The Relationship

Multi-core processors are likely to be a point of no return to meet the unending demand for increasing computational power. Nevertheless, the physical interconnection of many cores might currently represent the bottleneck toward kilo-core architectures. Optical wireless networks on-chip are therefore being considered as promising solutions to overcome the technological limits of wired interconnects. In this work, the spatial properties of the on-chip wireless channel are investigated through a ray tracing approach applied to a layered representation of the chip structure, highlighting the relationship between path loss, antenna positions and radiation properties.

scholarly journals Exploring a New Adaptive Routing Based on the Dijkstra Algorithm in Optical Networks-on-Chip

Micromachines ◽  
2021 ◽  
Vol 12 (1) ◽  
pp. 54
Author(s):  
Yan-Li Zheng ◽  
Ting-Ting Song ◽  
Jun-Xiong Chai ◽  
Xiao-Ping Yang ◽  
Meng-Meng Yu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Power Control ◽  
Optical Networks ◽  
Output Power ◽  
Network Performance ◽  
Transmission Loss ◽  
Adaptive Routing ◽  
Dijkstra Algorithm ◽  
Networks On Chip ◽  
On Chip

The photoelectric hybrid network has been proposed to achieve the ultrahigh bandwidth, lower delay, and less power consumption for chip multiprocessor (CMP) systems. However, a large number of optical elements used in optical networks-on-chip (ONoCs) generate high transmission loss which will influence network performance severely and increase power consumption. In this paper, the Dijkstra algorithm is adopted to realize adaptive routing with minimum transmission loss of link and reduce the output power of the link transmitter in mesh-based ONoCs. The numerical simulation results demonstrate that the transmission loss of a link in optimized power control based on the Dijkstra algorithm could be maximally reduced compared with traditional power control based on the dimensional routing algorithm. Additionally, it has a greater advantage in saving the average output power of optical transmitter compared to the adaptive power control in previous studies, while the network size expands. With the aid of simulation software OPNET, the network performance simulations in an optimized network revealed that the end-to-end (ETE) latency and throughput are not vastly reduced in regard to a traditional network. Hence, the optimized power control proposed in this paper can greatly reduce the power consumption of s network without having a big impact on network performance.

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