Fast evaluation of protocol processor architectures for IPv6 routing

2005 ◽  
Author(s):  
J. Lilius ◽  
D. Truscan ◽  
S. Virtanen
Keyword(s):  
Fast Evaluation ◽  
Processor Architectures

Urban Railway Bridge Fast Evaluation Based on Cloud Computing

2011 ◽  
Vol 71-78 ◽  
pp. 4501-4505
Author(s):  
Ming Chen ◽  
Wan Zhou
Keyword(s):  
Neural Networks ◽  
Cloud Computing ◽  
Model Updating ◽  
Condition Assessment ◽  
Fe Model ◽  
Railway Bridge ◽  
Fast Evaluation ◽  
Railway Bridges ◽  
Computing Model ◽  
Bridge Condition Assessment

Although modern bridge are carefully designed and well constructed, damage may occur in them due to unexpected causes. Currently, many different techniques have been proposed and investigated in bridge condition assessment. However, evaluation efficiency of condition assessment has not been paid much attention by the researchers. A fast evaluation of the urban railway bridge condition based on the cloud computing is presented. In this paper dynamic FE model and Artificial neural networks technique is applied to model updating. The cloud computing model provides the basis for fast analyses. It was found that when applied to the actually railway bridges, the proposed method provided results similar to those obtained by experts, but can improve efficiency of bridge

scholarly journals Reduced basis approximations of the solutions to spectral fractional diffusion problems

2020 ◽  
Vol 28 (3) ◽  
pp. 147-160
Author(s):  
Andrea Bonito ◽  
Diane Guignard ◽  
Ashley R. Zhang
Keyword(s):  
Computational Cost ◽  
Fractional Power ◽  
Reaction Diffusion ◽  
Fractional Diffusion ◽  
Diffusion Problem ◽  
Quadrature Point ◽  
Reduced Basis ◽  
Fast Evaluation ◽  
Bottle Neck ◽  
Diffusion Problems

AbstractWe consider the numerical approximation of the spectral fractional diffusion problem based on the so called Balakrishnan representation. The latter consists of an improper integral approximated via quadratures. At each quadrature point, a reaction–diffusion problem must be approximated and is the method bottle neck. In this work, we propose to reduce the computational cost using a reduced basis strategy allowing for a fast evaluation of the reaction–diffusion problems. The reduced basis does not depend on the fractional power s for 0 < smin ⩽ s ⩽ smax < 1. It is built offline once for all and used online irrespectively of the fractional power. We analyze the reduced basis strategy and show its exponential convergence. The analytical results are illustrated with insightful numerical experiments.

scholarly journals Efficient local locking for massively multithreaded in-memory hash-based operators

2021 ◽  
Author(s):  
Bashar Romanous ◽  
Skyler Windh ◽  
Ildar Absalyamov ◽  
Prerna Budhkar ◽  
Robert Halstead ◽  
...  
Keyword(s):  
Relational Databases ◽  
Aggregation Operators ◽  
Main Memory ◽  
Paradigm Shifts ◽  
Multithreaded Processors ◽  
Cache Hierarchies ◽  
Processor Architectures ◽  
Spatial Locality ◽  
Content Addressable Memories ◽  
Multi Core Processor

AbstractThe join and group-by aggregation are two memory intensive operators that are affecting the performance of relational databases. Hashing is a common approach used to implement both operators. Recent paradigm shifts in multi-core processor architectures have reinvigorated research into how the join and group-by aggregation operators can leverage these advances. However, the poor spatial locality of the hashing approach has hindered performance on multi-core processor architectures which rely on using large cache hierarchies for latency mitigation. Multithreaded architectures can better cope with poor spatial locality by masking memory latency with many outstanding requests. Nevertheless, the number of parallel threads, even in the most advanced multithreaded processors, such as UltraSPARC, is not enough to fully cover the main memory access latency. In this paper, we explore the hardware re-configurability of FPGAs to enable deeper execution pipelines that maintain hundreds (instead of tens) of outstanding memory requests across four FPGAs-drastically increasing concurrency and throughput. We present two end-to-end in-memory accelerators for the join and group-by aggregation operators using FPGAs. Both accelerators use massive multithreading to mask long memory delays of traversing linked-list data structures, while concurrently managing hundreds of thread states across four FPGAs locally. We explore how content addressable memories can be intermixed within our multithreaded designs to act as a synchronizing cache, which enforces locks and merges jobs together before they are written to memory. Throughput results for our hash-join operator accelerator show a speedup between 2$$\times $$ × and 3.4$$\times $$ × over the best multi-core approaches with comparable memory bandwidths on uniform and skewed datasets. The accelerator for the hash-based group-by aggregation operator demonstrates that leveraging CAMs achieves average speedup of 3.3$$\times $$ × with a best case of 9.4$$\times $$ × in terms of throughput over CPU implementations across five types of data distributions.

scholarly journals Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 516
Author(s):  
Tram Thi Bao Nguyen ◽  
Tuy Nguyen Tan ◽  
Hanho Lee
Keyword(s):  
Wireless Communication ◽  
High Throughput ◽  
Low Complexity ◽  
Ldpc Decoder ◽  
Processor Architectures ◽  
New Radio ◽  
Decoder Architecture ◽  
Check Node ◽  
Information Update ◽  
Wireless Standards

This paper presents a pipelined layered quasi-cyclic low-density parity-check (QC-LDPC) decoder architecture targeting low-complexity, high-throughput, and efficient use of hardware resources compliant with the specifications of 5G new radio (NR) wireless communication standard. First, a combined min-sum (CMS) decoding algorithm, which is a combination of the offset min-sum and the original min-sum algorithm, is proposed. Then, a low-complexity and high-throughput pipelined layered QC-LDPC decoder architecture for enhanced mobile broadband specifications in 5G NR wireless standards based on CMS algorithm with pipeline layered scheduling is presented. Enhanced versions of check node-based processor architectures are proposed to improve the complexity of the LDPC decoders. An efficient minimum-finder for the check node unit architecture that reduces the hardware required for the computation of the first two minima is introduced. Moreover, a low complexity a posteriori information update unit architecture, which only requires one adder array for their operations, is presented. The proposed architecture shows significant improvements in terms of area and throughput compared to other QC-LDPC decoder architectures available in the literature.

scholarly journals Color Image Evaluation for Small Space Based on FA and GEP

2014 ◽  
Vol 2014 ◽  
pp. 1-11
Author(s):  
Li Deng ◽  
Sui-Huai Yu ◽  
Wen-Jun Wang ◽  
Jun-Xuan Chen ◽  
Guo-Chang Liu
Keyword(s):  
Evaluation System ◽  
Frequency Conversion ◽  
Evaluation Method ◽  
Color Image ◽  
Gene Expression Programming ◽  
Image Evaluation ◽  
Evaluation Tool ◽  
Small Space ◽  
Entropy Weight ◽  
Fast Evaluation

Aiming at the problem that color image is difficult to quantify, this paper proposes an evaluation method of color image for small space based on factor analysis (FA) and gene expression programming (GEP) and constructs a correlation model between color image factors and comprehensive color image. The basic color samples of small space and color images are evaluated by semantic differential method (SD method), color image factors are selected via dimension reduction in FA, factor score function is established, and by combining the entropy weight method to determine each factor weights then the comprehensive color image score is calculated finally. The best fitting function between color image factors and comprehensive color image is obtained by GEP algorithm, which can predict the users’ color image values. A color image evaluation system for small space is developed based on this model. The color evaluation of a control room on AC frequency conversion rig is taken as an example, verifying the effectiveness of the proposed method. It also can assist the designers in other color designs and provide a fast evaluation tool for testing users’ color image.

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