Network processing challenges and an experimental NPU platform [network processor unit]

2003 ◽  
Author(s):  
P.G. Paulin ◽  
C. Pilkington ◽  
E. Bensoudane
Keyword(s):  
Network Processor ◽  
Processor Unit ◽  
Network Processing

scholarly journals An Approach to the Construction of a Network Processing Unit

2019 ◽  
Vol 26 (1) ◽  
pp. 39-62
Author(s):  
Stanislav O. Bezzubtsev ◽  
Vyacheslav V. Vasin ◽  
Dmitry Yu. Volkanov ◽  
Shynar R. Zhailauova ◽  
Vladislav A. Miroshnik ◽  
...  
Keyword(s):  
Simulation Model ◽  
General Purpose ◽  
Network Processor ◽  
Processing Unit ◽  
Use Case ◽  
General Purpose Processor ◽  
Software Products ◽  
Processor Architectures ◽  
Advantages And Disadvantages ◽  
Processor Unit

The paper proposes the architecture and basic requirements for a network processor for OpenFlow switches of software-defined networks. An analysis of the architectures of well-known network processors is presented − NP-5 from EZchip (now Mellanox) and Tofino from Barefoot Networks. The advantages and disadvantages of two different versions of network processor architectures are considered: pipeline-based architecture, the stages of which are represented by a set of general-purpose processor cores, and pipeline-based architecture whose stages correspond to cores specialized for specific packet processing operations. Based on a dedicated set of the most common use case scenarios, a new architecture of the network processor unit (NPU) with functionally specialized pipeline stages was proposed. The article presents a description of the simulation model of the NPU of the proposed architecture. The simulation model of the network processor is implemented in C ++ languages using SystemC, the open-source C++ library. For the functional testing of the obtained NPU model, the described use case scenarios were implemented in C. In order to evaluate the performance of the proposed NPU architecture a set of software products developed by KM211 company and the KMX32 family of microcontrollers were used. Evaluation of NPU performance was made on the basis of a simulation model. Estimates of the processing time of one packet and the average throughput of the NPU model for each scenario are obtained.

scholarly journals Multi-sensor capture and network processing for virtual reality conferencing

2019 ◽  
Author(s):  
Sylvie Dijkstra-Soudarissanane ◽  
Karim El Assal ◽  
Simon Gunkel ◽  
Frank ter Haar ◽  
Rick Hindriks ◽  
...  
Keyword(s):  
Virtual Reality ◽  
Network Processing

scholarly journals Smart Video Surveillance System Based on Edge Computing

Sensors ◽  
2021 ◽  
Vol 21 (9) ◽  
pp. 2958
Author(s):  
Antonio Carlos Cob-Parro ◽  
Cristina Losada-Gutiérrez ◽  
Marta Marrón-Romera ◽  
Alfredo Gardel-Vicente ◽  
Ignacio Bravo-Muñoz
Keyword(s):  
Computer Vision ◽  
Video Surveillance ◽  
Surveillance System ◽  
Video Surveillance System ◽  
Smart Camera ◽  
People Detection ◽  
Camera System ◽  
Edge Node ◽  
New Processing ◽  
Processor Unit

New processing methods based on artificial intelligence (AI) and deep learning are replacing traditional computer vision algorithms. The more advanced systems can process huge amounts of data in large computing facilities. In contrast, this paper presents a smart video surveillance system executing AI algorithms in low power consumption embedded devices. The computer vision algorithm, typical for surveillance applications, aims to detect, count and track people’s movements in the area. This application requires a distributed smart camera system. The proposed AI application allows detecting people in the surveillance area using a MobileNet-SSD architecture. In addition, using a robust Kalman filter bank, the algorithm can keep track of people in the video also providing people counting information. The detection results are excellent considering the constraints imposed on the process. The selected architecture for the edge node is based on a UpSquared2 device that includes a vision processor unit (VPU) capable of accelerating the AI CNN inference. The results section provides information about the image processing time when multiple video cameras are connected to the same edge node, people detection precision and recall curves, and the energy consumption of the system. The discussion of results shows the usefulness of deploying this smart camera node throughout a distributed surveillance system.

scholarly journals Room-temperature control and electrical readout of individual nitrogen-vacancy nuclear spins

2021 ◽  
Vol 12 (1) ◽  
Author(s):  
Michal Gulka ◽  
Daniel Wirtitsch ◽  
Viktor Ivády ◽  
Jelle Vodnik ◽  
Jaroslav Hruby ◽  
...  
Keyword(s):  
Dipolar Interaction ◽  
Coherence Time ◽  
Wide Bandgap ◽  
Nitrogen Vacancy ◽  
Ambient Conditions ◽  
Nuclear Spins ◽  
Quantum Device ◽  
Nanoscale Electronics ◽  
Quantum Processor ◽  
Processor Unit

AbstractNuclear spins in semiconductors are leading candidates for future quantum technologies, including quantum computation, communication, and sensing. Nuclear spins in diamond are particularly attractive due to their long coherence time. With the nitrogen-vacancy (NV) centre, such nuclear qubits benefit from an auxiliary electronic qubit, which, at cryogenic temperatures, enables probabilistic entanglement mediated optically by photonic links. Here, we demonstrate a concept of a microelectronic quantum device at ambient conditions using diamond as wide bandgap semiconductor. The basic quantum processor unit – a single 14N nuclear spin coupled to the NV electron – is read photoelectrically and thus operates in a manner compatible with nanoscale electronics. The underlying theory provides the key ingredients for photoelectric quantum gate operations and readout of nuclear qubit registers. This demonstration is, therefore, a step towards diamond quantum devices with a readout area limited by inter-electrode distance rather than by the diffraction limit. Such scalability could enable the development of electronic quantum processors based on the dipolar interaction of spin-qubits placed at nanoscopic proximity.

scholarly journals Architecture-Accuracy Co-optimization of ReRAM-based Low-cost Neural Network Processor

2020 ◽  
Author(s):  
Segi Lee ◽  
Sugil Lee ◽  
Jongeun Lee ◽  
Jong-Moon Choi ◽  
Do-Wan Kwon ◽  
...  
Keyword(s):  
Neural Network ◽  
Low Cost ◽  
Network Processor
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