CASPER: Concurrent hardware-software co-synthesis of hard real-time aperiodic and periodic specifications of embedded system architectures

This paper presents a protocol to support hard real-time traffic of end-to-end communication over non real-time LAN technology. The network is set up with nodes and switches, and real-time communication is handled by software (protocol) added between the Ethernet protocols and the TCP/IP suite. The proposed protocol establishes a virtual circuit based on admission control and manages hard real-time traffic to bypass the TCP/IP stack. This makes considerably reduce the dwell time in the nodes, and increase the achievable data frame rate. After the bypassing, traffic schedule is performed according to dynamic-priority EDF algorithm. The work does not need any modifications in the Ethernet hardware and coexists with TCP/IP suites, and then the LAN with the protocol can be connected to any existing Ethernet networks. It can be adopted in industrial hard real-time applications such as embedded systems, distributed control systems, parallel signal processing and robotics. We have performed some experiments to evaluate the protocol. Compared to some conventional hard real-time network protocols, the proposed one has better real-time performances and meets the requirements of reliability for hard real-time systems.

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Weighted Record Sample for Underwater Seismic Monitoring Application

10.29007/flck ◽

2019 ◽

Author(s):

Hussain Albarakati ◽

Reda Ammar ◽

Raafat Elfouly

Keyword(s):

Embedded System ◽

Information Extraction ◽

Real Time ◽

New Technology ◽

Seismic Monitoring ◽

Advanced Technology ◽

Oil Well ◽

System Architectures ◽

Research Activities ◽

Acoustic Sensor Networks

Underwater acoustic sensor networks have been developed as a new technology for real-time underwater applications, including seismic monitoring, disaster prevention, and oil well inspection. Unfortunately, this new technology is constrained to data sensing, large-volume transmission, and forwarding. As a result, the transmission of large volumes of data is costly in terms of both time and power. We thus focused our research activities on the development of embedded underwater computing systems. In this advanced technology, information extraction is performed underwater using data mining techniques or compression algorithms. We previously presented a new set of real-time underwater embedded system architectures that can manage multiple network configurations. In this study, we extend our research to develop information extraction for seismic monitoring underwater application to meet real-time constraints. The system performance is measured in terms of the minimum end-to-end delay and power consumption. The simulation results are presented to measure the performance of our architecture based on the information extraction algorithm.

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A Real-Time Capable Dynamic Partial Reconfiguration System for an Application-Specific Soft-Core Processor

International Journal of Reconfigurable Computing ◽

10.1155/2019/4723838 ◽

2019 ◽

Vol 2019 ◽

pp. 1-14

Author(s):

Michael Kirchhoff ◽

Philipp Kerling ◽

Detlef Streitferdt ◽

Wolfgang Fengler

Keyword(s):

Embedded System ◽

Real Time ◽

Soft Core ◽

Practical Implementation ◽

Full Potential ◽

Partial Reconfiguration ◽

Dynamic Partial Reconfiguration ◽

Wide Range ◽

Hard Real Time ◽

Application Specific

Modern FPGAs (Field Programmable Gate Arrays) are becoming increasingly important when it comes to embedded system development. Within these FPGAs, soft-core processors are often used to solve a wide range of different tasks. Soft-core processors are a cost-effective and time-efficient way to realize embedded systems. When using the full potential of FPGAs, it is possible to dynamically reconfigure parts of them during run time without the need to stop the device. This feature is called dynamic partial reconfiguration (DPR). If the DPR approach is to be applied in a real-time application-specific soft-core processor, an architecture must be created that ensures strict compliance with the real-time constraint at all times. In this paper, a novel method that addresses this problem is introduced, and its realization is described. In the first step, an application-specializable soft-core processor is presented that is capable of solving problems while adhering to hard real-time deadlines. This is achieved by the full design time analyzability of the soft-core processor. Its special architecture and other necessary features are discussed. Furthermore, a method for the optimized generation of partial bitstreams for the DPR as well as its practical implementation in a tool is presented. This tool is able to minimize given bitstreams with the help of a differential frame bitmap. Experiments that realize the DPR within the soft-core framework are presented, with respect to the need for hard real-time capability. Those experiments show a significant resource reduction of about 40% compared to a functionally equivalent non-DPR design.

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