Application Behavior Mapping across Heterogeneous Hardware Platforms

Author(s):  
Haifeng Chen ◽  
Hui Kang ◽  
Guofei Jiang ◽  
Kenji Yoshihira
2021 ◽  
Vol 31 (2) ◽  
pp. 1-26
Author(s):  
Quang Anh Pham Nguyen ◽  
Philipp Andelfinger ◽  
Wen Jun Tan ◽  
Wentong Cai ◽  
Alois Knoll

Spiking neural networks (SNN) are among the most computationally intensive types of simulation models, with node counts on the order of up to 10 11 . Currently, there is intensive research into hardware platforms suitable to support large-scale SNN simulations, whereas several of the most widely used simulators still rely purely on the execution on CPUs. Enabling the execution of these established simulators on heterogeneous hardware allows new studies to exploit the many-core hardware prevalent in modern supercomputing environments, while still being able to reproduce and compare with results from a vast body of existing literature. In this article, we propose a transition approach for CPU-based SNN simulators to enable the execution on heterogeneous hardware (e.g., CPUs, GPUs, and FPGAs), with only limited modifications to an existing simulator code base and without changes to model code. Our approach relies on manual porting of a small number of core simulator functionalities as found in common SNN simulators, whereas the unmodified model code is analyzed and transformed automatically. We apply our approach to the well-known simulator NEST and make a version executable on heterogeneous hardware available to the community. Our measurements show that at full utilization, a single GPU achieves the performance of about 9 CPU cores. A CPU-GPU co-execution with load balancing is also demonstrated, which shows better performance compared to CPU-only or GPU-only execution. Finally, an analytical performance model is proposed to heuristically determine the optimal parameters to execute the heterogeneous NEST.


2014 ◽  
Author(s):  
Paul A. Fox ◽  
Stephen T. Kozacik ◽  
John R. Humphrey ◽  
Aaron Paolini ◽  
Aryeh Kuller ◽  
...  

2020 ◽  
Vol 102 ◽  
pp. 514-523
Author(s):  
Jie Tang ◽  
Shaoshan Liu ◽  
Jie Cao ◽  
Dawei Sun ◽  
Bolin Ding ◽  
...  

Ergodesign ◽  
2020 ◽  
Vol 2020 (1) ◽  
pp. 19-24
Author(s):  
Igor Pestov ◽  
Polina Shinkareva ◽  
Sofia Kosheleva ◽  
Maxim Burmistrov

This article aims to develop a hardware-software system for access control and management based on the hardware platforms Arduino Uno and Raspberry Pi. The developed software and hardware system is designed to collect data and store them in the database. The presented complex can be carried and used anywhere, which explains its high mobility.


2021 ◽  
Vol 10 (1) ◽  
pp. 13
Author(s):  
Claudia Campolo ◽  
Giacomo Genovese ◽  
Antonio Iera ◽  
Antonella Molinaro

Several Internet of Things (IoT) applications are booming which rely on advanced artificial intelligence (AI) and, in particular, machine learning (ML) algorithms to assist the users and make decisions on their behalf in a large variety of contexts, such as smart homes, smart cities, smart factories. Although the traditional approach is to deploy such compute-intensive algorithms into the centralized cloud, the recent proliferation of low-cost, AI-powered microcontrollers and consumer devices paves the way for having the intelligence pervasively spread along the cloud-to-things continuum. The take off of such a promising vision may be hurdled by the resource constraints of IoT devices and by the heterogeneity of (mostly proprietary) AI-embedded software and hardware platforms. In this paper, we propose a solution for the AI distributed deployment at the deep edge, which lays its foundation in the IoT virtualization concept. We design a virtualization layer hosted at the network edge that is in charge of the semantic description of AI-embedded IoT devices, and, hence, it can expose as well as augment their cognitive capabilities in order to feed intelligent IoT applications. The proposal has been mainly devised with the twofold aim of (i) relieving the pressure on constrained devices that are solicited by multiple parties interested in accessing their generated data and inference, and (ii) and targeting interoperability among AI-powered platforms. A Proof-of-Concept (PoC) is provided to showcase the viability and advantages of the proposed solution.


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