HFMV: Hybridizing Formal Methods and Machine Learning for Verification of Analog and Mixed-Signal Circuits

Mixed-signal circuits for embedded machine-learning applications

2015 49th Asilomar Conference on Signals, Systems and Computers ◽

10.1109/acssc.2015.7421361 ◽

2015 ◽

Cited By ~ 19

Author(s):

B. Murmann ◽

D. Bankman ◽

E. Chai ◽

D. Miyashita ◽

L. Yang

Keyword(s):

Machine Learning ◽

Mixed Signal ◽

Mixed Signal Circuits ◽

Machine Learning Applications

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Automatic Surrogate Model Generation and Debugging of Analog/Mixed-Signal Designs Via Collaborative Stimulus Generation and Machine Learning

Proceedings of the 26th Asia and South Pacific Design Automation Conference ◽

10.1145/3394885.3431544 ◽

2021 ◽

Author(s):

Jun Yang Lei ◽

Abhijit Chatterjee

Keyword(s):

Machine Learning ◽

Surrogate Model ◽

Model Generation ◽

Mixed Signal ◽

Stimulus Generation

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Towards Neuromorphic Learning Machines Using Emerging Memory Devices with Brain-Like Energy Efficiency

Journal of Low Power Electronics and Applications ◽

10.3390/jlpea8040034 ◽

2018 ◽

Vol 8 (4) ◽

pp. 34 ◽

Cited By ~ 10

Author(s):

Vishal Saxena ◽

Xinyu Wu ◽

Ira Srivastava ◽

Kehan Zhu

Keyword(s):

Machine Learning ◽

Energy Efficiency ◽

Deep Learning ◽

Large Scale ◽

Learning Algorithms ◽

Memory Devices ◽

Cognitive Computing ◽

Mixed Signal ◽

Von Neumann ◽

Emerging Memory

The ongoing revolution in Deep Learning is redefining the nature of computing that is driven by the increasing amount of pattern classification and cognitive tasks. Specialized digital hardware for deep learning still holds its predominance due to the flexibility offered by the software implementation and maturity of algorithms. However, it is being increasingly desired that cognitive computing occurs at the edge, i.e., on hand-held devices that are energy constrained, which is energy prohibitive when employing digital von Neumann architectures. Recent explorations in digital neuromorphic hardware have shown promise, but offer low neurosynaptic density needed for scaling to applications such as intelligent cognitive assistants (ICA). Large-scale integration of nanoscale emerging memory devices with Complementary Metal Oxide Semiconductor (CMOS) mixed-signal integrated circuits can herald a new generation of Neuromorphic computers that will transcend the von Neumann bottleneck for cognitive computing tasks. Such hybrid Neuromorphic System-on-a-chip (NeuSoC) architectures promise machine learning capability at chip-scale form factor, and several orders of magnitude improvement in energy efficiency. Practical demonstration of such architectures has been limited as performance of emerging memory devices falls short of the expected behavior from the idealized memristor-based analog synapses, or weights, and novel machine learning algorithms are needed to take advantage of the device behavior. In this article, we review the challenges involved and present a pathway to realize large-scale mixed-signal NeuSoCs, from device arrays and circuits to spike-based deep learning algorithms with ‘brain-like’ energy-efficiency.

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