Inductive verification of iterative systems

M-groupoid as a tool for investigating mathematical models of computers

Fundamenta Informaticae ◽

10.3233/fi-1977-1107 ◽

1977 ◽

Vol 1 (1) ◽

pp. 71-91

Author(s):

Jerzy Tiuryn

Keyword(s):

Mathematical Models ◽

Simple Approximation ◽

Simplified Model ◽

Suitable Choice ◽

Iterative Systems

An M-groupoid is a simplified model of computer. The classes of M-groupoids, address machines, stored program computers and iterative systems are presented as categories – by a suitable choice of homomorphisms. It is shown that the first three categories are equivalent, whereas the fourth is weaker (it is not equivalent to the previous ones and it can easily be embedded in the category of M-groupoids). This fact proves that M-groupoids form an essentially better and reasonably simple approximation of more complicated models of computers than iterative systems.

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On the Question of Asymptotic Integration of Singularly Perturbed Fractional-Order Problems

Asian Journal of Fuzzy and Applied Mathematics ◽

10.24203/ajfam.v6i3.5600 ◽

2018 ◽

Vol 6 (3) ◽

Author(s):

Burkhan Kalimbetov

Keyword(s):

Differential Equations ◽

Small Parameter ◽

Fractional Order ◽

Initial Problem ◽

Singularly Perturbed ◽

Asymptotic Integration ◽

Partial Derivatives ◽

Systems Of Differential Equations ◽

Regularization Problem ◽

Iterative Systems

In this paper we consider an initial problem for systems of differential equations of fractional order with a small parameter for the derivative. Regularization problem is produced, and algorithm for normal and unique solubility of general iterative systems of differential equations with partial derivatives is given.Â

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A high throughput architecture for a low complexity soft-output demapping algorithm

Advances in Radio Science ◽

10.5194/ars-13-73-2015 ◽

2015 ◽

Vol 13 ◽

pp. 73-80 ◽

Cited By ~ 1

Author(s):

I. Ali ◽

U. Wasenmüller ◽

N. Wehn

Keyword(s):

Wireless Communication ◽

High Throughput ◽

Turbo Code ◽

Low Complexity ◽

Implementation Cost ◽

Qam Modulation ◽

Iterative Systems ◽

Very High ◽

Complexity Algorithm ◽

Hardware Performance

Abstract. Iterative channel decoders such as Turbo-Code and LDPC decoders show exceptional performance and therefore they are a part of many wireless communication receivers nowadays. These decoders require a soft input, i.e., the logarithmic likelihood ratio (LLR) of the received bits with a typical quantization of 4 to 6 bits. For computing the LLR values from a received complex symbol, a soft demapper is employed in the receiver. The implementation cost of traditional soft-output demapping methods is relatively large in high order modulation systems, and therefore low complexity demapping algorithms are indispensable in low power receivers. In the presence of multiple wireless communication standards where each standard defines multiple modulation schemes, there is a need to have an efficient demapper architecture covering all the flexibility requirements of these standards. Another challenge associated with hardware implementation of the demapper is to achieve a very high throughput in double iterative systems, for instance, MIMO and Code-Aided Synchronization. In this paper, we present a comprehensive communication and hardware performance evaluation of low complexity soft-output demapping algorithms to select the best algorithm for implementation. The main goal of this work is to design a high throughput, flexible, and area efficient architecture. We describe architectures to execute the investigated algorithms. We implement these architectures on a FPGA device to evaluate their hardware performance. The work has resulted in a hardware architecture based on the figured out best low complexity algorithm delivering a high throughput of 166 Msymbols/second for Gray mapped 16-QAM modulation on Virtex-5. This efficient architecture occupies only 127 slice registers, 248 slice LUTs and 2 DSP48Es.

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