Dynamic Fair Cache Partitioning for Chip Multiprocessor

Dynamic Partition of Shared Cache for Multi-Thread Application in Multi-Core System

Key Engineering Materials ◽

10.4028/www.scientific.net/kem.439-440.1587 ◽

2010 ◽

Vol 439-440 ◽

pp. 1587-1594

Author(s):

Shuo Li ◽

Feng Wu

Keyword(s):

System Performance ◽

Scientific Computing ◽

Chip Multiprocessor ◽

Core System ◽

Cache Partitioning ◽

Shared Cache ◽

Rate Information ◽

Partitioning Algorithm ◽

Cache Partition

In a chip-multiprocessor with a shared cache structure , the competing accesses from different applications degrade the system performance.The accesses degrade the performance and result in non-predicting executing time. Cache partitioning techniques can exclusively partition the shared cache among multiple competing applications. In this paper, the authors design the framework of Process priority-based Multithread Cache Partitioning(PP-MCP),a dynamic shared cache partitioning mechanism to improve the performance of multi-threaded multi-programmed workloads. The framework includes a miss rate monitor , called Application-oriented Miss Rate Monitor (AMRM) , which dynamically collect s miss rate information of multiple multi-threaded applications on different cache partitions , and process priority-based weighted cache partitioning algorithm ,which extends traditional miss rate oriented cache partition algorithms.The algorithm allocates Cache in sequence of the value of the process priority and it ensures that the highest priority process will get enough Cache space; and the applications with more threads tend to get more shared cache in order to improve t he overall system performance. Experiments show that PP-MCP has better IPC throughput and weighted speedup. Specifically , for multi-threaded multi-programmed scientific computing workloads , PP-MCP-1 improves throughput by up to 20% and on average 10 % over PP-MCP-0.

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The Review of Cache Partitioning in Multi-Core Processor

Key Engineering Materials ◽

10.4028/www.scientific.net/kem.439-440.1223 ◽

2010 ◽

Vol 439-440 ◽

pp. 1223-1229

Author(s):

Shuo Li ◽

Gao Chao Xu ◽

Yu Shuang Dong ◽

Feng Wu

Keyword(s):

System Performance ◽

Optimal Performance ◽

Chip Multiprocessor ◽

Future Research ◽

Multicore Processor ◽

Cache Partitioning ◽

Shared Cache ◽

Microelectronics Technology ◽

Multi Core Processor ◽

Cache Pollution

With the development of microelectronics technology, Chip Multi-Processor (CMP) or multi-core design has become a mainstream choice for major microprocessor vendors. But in a chip-multiprocessor with a shared cache structure , the competing accesses from different applications degrade the system performance , resulting in non-optimal performance and non-predicting executing time. Cache partitioning techniques can exclusively partition the shared cache among multiple competing applications. In this paper, we first introduce the problems caused by Cache pollution in multicore processor structure; then present the different methods of Cache partitioning in multicore processor structure¬ －－categorizing them based on the different metrics. And finally, we discuss some possible directions for future research in the area.

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