HDL Design Architecture for Compatible Multichannel Multi-frequency Rate SERIAL Bit Error Rate Tester (BERT) ASIC IP Core for Testing of High Speed Wireless System Products/Applications

2015 ◽  
Author(s):  
P.N.V.M. Sastry ◽  
D.N. Rao ◽  
S. Vathsal ◽  
A. Rajaiah
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
High Speed ◽  
Ip Core ◽  
Wireless System ◽  
Frequency Rate

scholarly journals An identification of the tolerable time-interleaved analog-to-digital converter timing mismatch level in high-speed orthogonal frequency division multiplexing systems

2022 ◽  
Vol 12 (2) ◽  
pp. 1667
Author(s):  
Vo Trung Dung Huynh ◽  
Linh Mai ◽  
Hung Ngoc Do ◽  
Minh Ngoc Truong Nguyen ◽  
Trung Kien Pham
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Communication Systems ◽  
Orthogonal Frequency Division Multiplexing ◽  
High Speed ◽  
Performance Degradation ◽  
Frequency Division Multiplexing ◽  
Frequency Division ◽  
Analog To Digital ◽  
Time Interleaved

<span>High-speed Terahertz communication systems has recently employed orthogonal frequency division multiplexing approach as it provides high spectral efficiency and avoids inter-symbol interference caused by dispersive channels. Such high-speed systems require extremely high-sampling <br /> time-interleaved analog-to-digital converters at the receiver. However, timing mismatch of time-interleaved analog-to-digital converters significantly causes system performance degradation. In this paper, to avoid such performance degradation induced by timing mismatch, we theoretically determine maximum tolerable mismatch levels for orthogonal frequency division multiplexing communication systems. To obtain these levels, we first propose an analytical method to derive the bit error rate formula for quadrature and pulse amplitude modulations in Rayleigh fading channels, assuming binary reflected gray code (BRGC) mapping. Further, from the derived bit error rate (BER) expressions, we reveal a threshold of timing mismatch level for which error floors produced by the mismatch will be smaller than a given BER. Simulation results demonstrate that if we preserve mismatch level smaller than 25% of this obtained threshold, the BER performance degradation is smaller than 0.5 dB as compared to the case without timing mismatch.</span>

scholarly journals The Influence of Digital Modulations on 320 Gbit/s Optical Time Division Multiplexing

2015 ◽  
Vol 11 (4) ◽  
pp. 187
Author(s):  
Lukas Koci ◽  
Petr Munster ◽  
Tomas Horvath ◽  
Milan Cucka ◽  
Miloslav Filka
Keyword(s):  
Optical Fiber ◽  
Bit Error Rate ◽  
Error Rate ◽  
High Speed ◽  
Positive Influence ◽  
Modulation Formats ◽  
Time Division Multiplexing ◽  
Optical Time Division Multiplexing ◽  
Optical Time ◽  
Time Division

In this article the optical time division multiplexingtechnique for high speed point-to-point optical networksis discussed. We performed test of influence of selected types modulation formats in the optical time division multiplexing simulation model with a distance of 30 km. Additionally, this paper focuses on maximum bandwidth usage, improvement of bit error rate and the another goal is to achieve the maximal transmission distance by using of special compensation optical fiber. Optimal length of compensation optical fiber was found and used during simulations. We demonstrated positive influence compensation optical fiber on bit error rate. For comparisonof modulation formats such as return-to-zero, non-return-to-zero, chirped-return-to-zero, carrier-suppressed-return-to-zero, and m-ary quadrature amplitude modulation were tested. Our results confirm that it is possible to achieve better bit error rate for selected modulation formats.

scholarly journals Giga-bit VLBI Data Recorder, New Concept of Formatter Independent

1998 ◽  
Vol 164 ◽  
pp. 395-396
Author(s):  
J. Nakajima ◽  
Y. Koyama ◽  
M. Sekido ◽  
H. Kiuchi ◽  
S. Hama ◽  
...  
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Digital Technology ◽  
High Speed ◽  
High Performance ◽  
Scientific Field ◽  
Recording System ◽  
Digital Interface ◽  
Vlbi Data ◽  
Bit Stream

AbstractA high performance VLBI recorder project using advanced digital technology started in 1995. TOSHIBA GBR 1000 and VLBI interface define 32 parallel, 32 MHz clock standard digital interface and support transparent recording/play-back to extremely high-speed digital bit stream. This is the formatter independent scientific recording bind the UTC to observed data. This highly reliable, low-bit-error-rate (10−16) recording system is also expected to be used in other scientific field. For the first example to examine the recorder performance in VLBI, we had been prepared 1024 Mbps sampler (256/512/1024 MSps, 2 bit, 4/2/1 ch). And here, an experimental giga-bit correlator specification for these VLBI acquisition system is introduced.

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