FD-SOI Technology Development and Key Devices Characteristics for Fast, Power Efficient, Low Voltage SoCs

2014 ◽  
Author(s):  
Joel Hartmann
Keyword(s):  
Technology Development ◽  
Low Voltage ◽  
Power Efficient ◽  
Fast Power ◽  
Soi Technology

LOW-NOISE SILICON-ON-INSULATOR HALL DEVICES

2004 ◽  
Vol 04 (02) ◽  
pp. L345-L354 ◽  
Author(s):  
Y. HADDAB ◽  
V. MOSSER ◽  
M. LYSOWEC ◽  
J. SUSKI ◽  
L. DEMEUS ◽  
...  
Keyword(s):  
Noise Level ◽  
Low Voltage ◽  
Silicon Layer ◽  
Electrical Current ◽  
Low Noise ◽  
Silicon On Insulator ◽  
Technological Parameters ◽  
Wide Range ◽  
Hall Sensors ◽  
Soi Technology

Hall sensors are used in a very wide range of applications. A very demanding one is electrical current measurement for metering purposes. In addition to high precision and stability, a sufficiently low noise level is required. Cost reduction through sensor integration with low-voltage/low-power electronics is also desirable. The purpose of this work is to investigate the possible use of SOI (Silicon On Insulator) technology for this integration. We have fabricated SOI Hall devices exploring the useful range of silicon layer thickness and doping level. We show that noise is influenced by the presence of LOCOS and p-n depletion zones near the edges of the active zones of the devices. A proper choice of SOI technological parameters and process flow leads to up to 18 dB reduction in Hall sensor noise level. This result can be extended to many categories of devices fabricated using SOI technology.

Recent Progress in SOI Materials and Devices for VLSI Applications

1993 ◽  
Vol 316 ◽  
Author(s):  
H. H. Hosack
Keyword(s):  
High Performance ◽  
Large Scale ◽  
Recent Progress ◽  
Low Voltage ◽  
Silicon On Insulator ◽  
Significant Interest ◽  
Significant Performance ◽  
Cmos Ic ◽  
Bulk Processing ◽  
Soi Technology

Silicon-On-Insulator (SOI) technology [1-4] has been shown to have significant performance and fabrication advantages over conventional bulk processing for a wide variety of large scale CMOS IC applications. Advantages in radiation environments has generated significant interest in this technology from military and space science communities [5,6]. Possible advantages of SOI technology for low power, low voltage and high performance circuit applications is under serious consideration by several commercial IC manufacturers [7,8].

Low-voltage 0.35 μm CMOS/SOI technology for high-performance ASIC's

2002 ◽  
Author(s):  
A.O. Adan ◽  
T. Naka ◽  
S. Kaneko ◽  
D. Urabe ◽  
K. Higashi ◽  
...  
Keyword(s):  
High Performance ◽  
Low Voltage ◽  
Soi Technology

Fast power-efficient circuit-block switch-off scheme

2004 ◽  
Vol 40 (2) ◽  
pp. 103 ◽  
Author(s):  
S. Henzler ◽  
G. Georgakos ◽  
J. Berthold ◽  
D. Schmitt-Landsiedel
Keyword(s):  
Power Efficient ◽  
Fast Power

AN ULTRA LOW-VOLTAGE/POWER-EFFICIENT ALL-DIGITAL DELAY LOCKED LOOP IN 55 nm CMOS TECHNOLOGY

2012 ◽  
Vol 21 (08) ◽  
pp. 1240025 ◽  
Author(s):  
CHUN-YUAN CHENG ◽  
JINN-SHYAN WANG ◽  
CHENG-TAI YEH
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Cmos Technology ◽  
Maximum Frequency ◽  
Clock Frequency ◽  
Power Efficient ◽  
Delay Locked Loop ◽  
Measurement Results ◽  
Variation Tolerance

This paper presents an all-digital delay locked loop (ADDLL) that uses asynchronous-deskewing technology and achieves low power/voltage, small jitter, fast locking, and high process, voltage, and temperature (PVT)-variation tolerance. The measurement results show that the maximum frequency is 100 MHz at 0.35 V with 19 μW power dissipation, 62 ps peak-to-peak jitter, and 3 locking cycles. When operated at 0.5 V, the measured maximal operating clock frequency is 450 MHz with 12 ps peak-to-peak jitter, 6 locking cycles and 119 μW power dissipation. The ADDLL is fabricated with 55 nm CMOS technology, and the active area is only 0.019 mm2.

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