An Efficient Task-Based Execution Model for Stochastic Linear Solver on Multi-core and Many-Core Systems

2015 ◽  
Author(s):  
Fan Ye ◽  
Christophe Calvin ◽  
Serge Petiton
Keyword(s):  
Linear Solver ◽  
Execution Model ◽  
Many Core

Architecture and Evaluation of Low Power Many-Core SoC with Two 32-Core Clusters

2014 ◽  
Vol E97.C (4) ◽  
pp. 360-368
Author(s):  
Takashi MIYAMORI ◽  
Hui XU ◽  
Hiroyuki USUI ◽  
Soichiro HOSODA ◽  
Toru SANO ◽  
...  
Keyword(s):  
Low Power ◽  
Many Core

Data Structure Directed Thread Partitioning Method and Execution Model

2014 ◽  
Vol 24 (10) ◽  
pp. 2432-2459
Author(s):  
Yan-Ning DU ◽  
Yin-Liang ZHAO ◽  
Bo HAN ◽  
Yuan-Cheng LI
Keyword(s):  
Data Structure ◽  
Execution Model ◽  
Thread Partitioning

Hierarchical Role-Based Delegation Authorization Execution Model for Service Grid

2009 ◽  
Vol 20 (9) ◽  
pp. 2495-2510 ◽  
Author(s):  
Zhi-Gang CHEN ◽  
Jin-Song GUI ◽  
Ying GUO
Keyword(s):  
Service Grid ◽  
Execution Model ◽  
Role Based

On Synchronization and Evaluation Method of Chipped Many-Core Processor

2010 ◽  
Vol 33 (10) ◽  
pp. 1777-1787 ◽  
Author(s):  
Wei-Zhi XU ◽  
Feng-Long SONG ◽  
Zhi-Yong LIU ◽  
Dong-Rui FAN ◽  
Lei YU ◽  
...  
Keyword(s):  
Evaluation Method ◽  
Many Core

Using Write Mask to Support Hybrid Write-Back and Write-Through Cache Policy on Many-Core Architectures

2009 ◽  
Vol 31 (11) ◽  
pp. 1918-1928 ◽  
Author(s):  
Wei LIN ◽  
Xiao-Chun YE ◽  
Feng-Long SONG ◽  
Hao ZHANG
Keyword(s):  
Many Core

Research on highly parallel embedded control system design and implementation method

Impact ◽  
2019 ◽  
Vol 2019 (10) ◽  
pp. 44-46
Author(s):  
Masato Edahiro ◽  
Masaki Gondo
Keyword(s):  
Computer Architecture ◽  
Intelligent Systems ◽  
Large Scale ◽  
General Purpose ◽  
Heterogeneous Structure ◽  
Single Chip ◽  
Powertrain Control ◽  
Processing Power ◽  
Hardware Description ◽  
Many Core

The pace of technology's advancements is ever-increasing and intelligent systems, such as those found in robots and vehicles, have become larger and more complex. These intelligent systems have a heterogeneous structure, comprising a mixture of modules such as artificial intelligence (AI) and powertrain control modules that facilitate large-scale numerical calculation and real-time periodic processing functions. Information technology expert Professor Masato Edahiro, from the Graduate School of Informatics at the Nagoya University in Japan, explains that concurrent advances in semiconductor research have led to the miniaturisation of semiconductors, allowing a greater number of processors to be mounted on a single chip, increasing potential processing power. 'In addition to general-purpose processors such as CPUs, a mixture of multiple types of accelerators such as GPGPU and FPGA has evolved, producing a more complex and heterogeneous computer architecture,' he says. Edahiro and his partners have been working on the eMBP, a model-based parallelizer (MBP) that offers a mapping system as an efficient way of automatically generating parallel code for multi- and many-core systems. This ensures that once the hardware description is written, eMBP can bridge the gap between software and hardware to ensure that not only is an efficient ecosystem achieved for hardware vendors, but the need for different software vendors to adapt code for their particular platforms is also eliminated.

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